TDG13 Search Results

Contextual Info: * 16:1 MULTIPLEXER SYNERGY SY10E164 SY100E164 SEMICONDUCTOR FEATURES • ■ 850ps Data Input to Output ■ Extended 100E V ee range of -4.2V to -5.5V ■ Differential output ■ Fully compatible with industry standard 10KH, 100K ECL levels DESCRIPTION The SY10/100E164 are 16:1 m ultiplexers with a

Contextual Info: SYNERGY SEMI CO NDUC TO R « 57E D • TQQiaöl 000G37S 754 SINGLE SUPPLY PECL-TTL 1:9 CLOCK DRIVER SYNERGY SEMICONDUCTOR AD VAN CE INFORMATION SY10H641 SY100H641 - r - S Z - 19 FEA TU R ES DESCRIPTION ■ P E C L -T T L version of popular ECLInPS E111 ■ Low skew

Contextual Info: « HEX D-LATCH SYNERGY SY100S350 SEMICONDUCTOR DESCRIPTION FEATURES • Max. transparent propagation delay of 900ps ■ Min. Master Reset and Enable pulse widths of 100ps ■ I ee mln. of -98m A ■ ESD protection of 2000V ■ Industry standard 100K ECL levels

TD013

Abstract: E143 SY100E143 SY10E143 SY10E143JC
Contextual Info: 9-BIT HOLD REGISTER SYNERGY SY10E143 SY100E143 S E M IC O N D U C T O R DESCRIPTION FEATURES • 700MHz min. operating frequency ■ Extended 100E VEE range of -4.2V to -5.5V ■ 9 bits wide for byte-parity applications ■ Asynchronous Master Reset ■ Dual clocks

SY100E171

Abstract: SY10E171 SY10E171JC
Contextual Info: * FEATURES D E S C R IP T IO N I 725ps max. D to output I Differential outputs i Split select architecture ESD protection of 2000V Fully compatible with Industry standard 10KH, 100K ECL levels Extended 100E V e e range of - 4 .2 V to -5 .4 6 V Internal 75KQ Input pulldown resistors

Contextual Info: ^ SINGLE SUPPLY PECL-TTL 1:4 CLOCK DRIVER SYNERGY SEMICONDUCTOR FEATURES preÏ m n a r v SY10100H842 DESCRIPTION • Translates positive ECL to TTL PECL-TTL ■ 300ps pin-to-pin skew ■ Guaranteed skew spec ■ Differential internal design for increased noise

Contextual Info: =1001381 * 0002213 3Û0 SYNERGY 8- b it s h i f t r e g i s t e r sy-ioos34i S E M IC O N D U C T O R FEATURES • ■ Max. shift frequency of 600MHz ■ Max. Clock to Q delay of 1200ps ■ Iee min. o f-150m A ■ ESD protection of 2000V ■ Industry standard 100K ECL levels

Contextual Info: ^ LOW POWER HEX TTL-tO-ECL TRANSLATOR SYNERGY SY100S324 SEMICONDUCTOR DESCRIPTION FEATURES The SY100S324 is a hex translator designed to convert TTL logic levels to 100K ECL levels. The inputs are TTL compatible with differential outputs that can either be used

Contextual Info: * 5-BIT REGISTERED TRANSCEIVER SYNERGY SY100S891 SEMICONDUCTOR DESCRIPTION FEATURES • 25 ohm cut-off bus outputs ■ 50 ohm receiver outputs ■ Transmit and receive registers with separate clocks ■ 1500ps max. delay from CLKi to Bus Outputs BUS ■ 1500ps max. delay from CLK2 to Receiver Outputs

Contextual Info: uIPL SYNERGY SEMICONDUCTOR PRELIMINARY TTL BICMOS STATIC RAM 64K 16KX 4-BIT V 1 FEATURES SY71B98-7 SY71B98-10 SY71B98-12 DESCRIPTION • ■ ■ ■ ■ Address access time, tA A : 7/10/12ns max. Chip select access time, tACS: 4/6/7ns max. Popular 16K x 4 with common I/O organization

Contextual Info: * LOW-POWER 9-BIT INVERTER SYNERGY SY100S321 SEMICONDUCTOR FEATURES DESCRIPTION • Max. propagation delay of 700ps ■ lEE mln. of -55mA ■ ESD protection of 2000 volts ■ Extended supply voltage option: — VEE = -4.2V to -5.46V ■ Voltage and temperature compensation for

FE2019

Contextual Info: DUAL PHASÉ LOCKED LOOP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • ■ ■ ■ 1.12GHz maximum VCO frequency 30 to 560MHz reference input operating frequency Frequency doubler mode Low jitter design ■ ■ ■ ■ PECL differential outputs PECL and TTL reference voltages available

Contextual Info: « SYNERGY SEMICONDUCTOR DUAL TTL-TO-DIFFERENTIAL PECL TRANSLATOR PRo b ^ SY100ELT22 iu u c li^ DESCRIPTION FEATURES 300ps typical propagation delay The SY10ELT/100ELT22 are dual TTL-to-differential PECL translators. Because PECL Positive ECL levels

Contextual Info: * 3-BIT SCANNABLE SYNERGY ADDRESS A U U K t b b DRIVER U K IV tH SEMICONDUCTOR FEATURES SY100E212 DESCRIPTION • ■ ■ ■ ■ ■ Scannable version E112 driver I025ps max. CLK to Output Dual differential outputs Master Reset Internal 75KQ input pull-down resistors

SY100S811

Abstract: SY100S811JC
Contextual Info: This Material Copyrighted By Its Respective Manufacturer C lo c k w o rk s PRELIMINARY SY100S811 SEM ICONDUCTOR B L O C K D IA G R A M P E C L D C E L E C T R IC A L C H A R A C T E R IS T IC S V c c = VCCO = 5 .0 V ± 5 % Ta = 0°C Parameter Min. Vbb

Contextual Info: * SYNERGY ULTRA-HIGH-SPEED 64-WORD x 18-BIT FIFO SEMICONDUCTOR PRELIMINARY SY69167 SY69267 DESCRIPTION FEATURES • System clock speeds to 200MHz ■ User-selectable bandwidth — one read or one write operation each clock cycle ■ Selectable O VERFLOW and UNDERFLOW Interrupts

SY101L484

Contextual Info: TD013Ö1 QDDD07C1 b27 S7E D SYNERGY SEMICONDUCTOR Address access time, tAA: 7/8/1 Ons max. Chip select access time, tAc: 3/4/5ns max. Eliminates write recovery glitch found on competitors’ ECL RAMs Low power supply current, I e e : -180m A min. Designed for alpha particle immunity

SY69612

Abstract: HP 85700A HP53132A
Contextual Info: * SONET/SDH/ATM OC-12 TRANSCEIVER SYNERGY SEMICONDUCTOR FEATURES PRELIMINARY INFORMATION SY69612 DESCRIPTION A complete SONET/SDH Transmitter & Receiver Complies with Bellcore, CCiTT and ANSI specifications On-chip PLL for clock generation SONET framing defeatable