T0013FLL Search Results

F100K

Abstract: SY100S341
Contextual Info: T0013fll « 0002213 3Û0 8-BIT SHIFT REGISTER SYNERGY SY100S341 S E M IC O N D U C T O R FEATURES • ■ Max. shift frequency of 600MHz ■ Max. Clock to Q delay of 1200ps ■ Iee min. of -150m A ■ ESD protection of 2000V ■ Industry standard 100K ECL levels

Contextual Info: SY100S366 9-BIT COMPARATOR SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • Max. propagation delay of I500ps ■ le e min. of-120mA ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option: — VEE = -4.2V to -5.46V

Contextual Info: V PRELIMINARY SY10ELT22L SY100ELT22L d u a l t t l -t o - d if f e r e n t ia l SYNERGY p e c l tr a n s la to r SEMICONDUCTOR DESCRIPTION FEATURES The SY10ELT/100ELT22L are dual TTL-to-differential PECL translators. Because PECL Positive ECL levels are used, only +3.3V and ground are required. The small

Contextual Info: * 12-BIT PARITY GENERATOR/CHECKER SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • ■ ■ ■ ■ ■ ■ ■ Provides odd-HIGH parity of 12 Inputs Output register with Shift/Hold capability 900ps max. D to Q/Q output Enable control Asynchronous Register Reset

Contextual Info: ^ e v u m r v S IN G L E s S S S Ê Ê S F S U P P L Y 1:4C L0C K D R IV ER p r e l i m i n a r y svittiooH 843 DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-TTL ■ 300ps pln-to-pin skew ■ Guaranteed skew spec ■ Differential internal design for increased noise

Contextual Info: * 5-BIT 2:1 MULTIPLEXER SYNERGY SY10E158 SY100E158 SEMICONDUCTOR FEATURES DESCRIPTION • ■ ■ ■ ■ 550ps max. D to output 775ps max. SEL to output Differential outputs ESD protection of 2000V Fully compatible with industry standard 10KH, 100K ECL levels

DG7-32

Contextual Info: * SYNERGY DATA S E P A R A TO R PRELIMINARY SY10E197 SEMICONDUCTOR FEATURES • ■ ■ ■ ■ ■ 2:7 and 1:7 RLL format-compatible Fully Integrated Vco for 50Mb/s operation External Vco input for higher operating frequency Anti-equivocation circuitry to ensure PLL lock

ET 8211

Abstract: tvccd 20 band equalizer twisted pair cable with parameter
Contextual Info: »es* SYNERGY A STS'3 ADAPT,VE EQUALIZER P R E L 'sY 6 7 6 7 2 SEMICONDUCTOR FEATURES DESCRIPTION • Adaptive Equalizer with Line Compensation Loop Control ■ Compiles with ATM Forum STS-3 Twisted Pair Specifications ■ Transmitter output disable option for quiet line

Contextual Info: * QUAD MULTIPLEXER/ LATCH SYNERGY SEMICONDUCTOR FEATURES SY100S355 DESCRIPTION • Max. propagation delay of 1100ps ■ Max. enable to output delay of I400ps ■ I ee min. of -80m A ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option:

Contextual Info: A LOW-POWER OCTAL ECL/TTL SYNERGY S SEMICONDUCTOR — W l IH L A I O n “ " I DESCRIPTION FEATURES • Bi-directional translation ■ ESD protection of 2000V ■ Latched outputs ■ Voltage compensated operating range: -4.2V to -5.7V ■ Fast TTL outputs

Contextual Info: * SYNERGY 2K X 9 ADVANCED SELF-TIMED SRAM SEMICONDUCTOR FEATURES • Extremely fast access times: tcHCH = 5/6ns max. ■ Extended supply voltage option: — Vee = -5.2V ■ Completely self-timed read and write cycle ■ On-chip input and output registers

Contextual Info: * SINGLE SUPPLY PECL-TTL 1:9 CLOCK DRIVER SYNERGY SEMICONDUCTOR Clockworks PRELIMINARY SY10/100H641 DESCRIPTION FEATURES • PECL-TTL version of popular ECLinPS E111 ■ Guaranteed low skew specification ■ Latch ■ Differential internal design ■ V bb output for single-ended operation

DALE crystal 16Mhz

Abstract: SY89429A SY89429AJC
Contextual Info: * Clockworks PRELIMINARY SY89429A FREQUENCY SYNTHESIZER SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • ■ ■ ■ ■ ■ ■ 25 to 400MHz differential PECL outputs 10ps rms max. jitter Minimal frequency over-shoot Synthesized architecture Serial 3 wire interface

SY100H841ZC

Abstract: SY10H841ZC
Contextual Info: This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer Clockworks PRELIMINARY SY10/100H841 SYNERGY S EM IC O N D U C TO R AC CHARACTERISTICS VT = VE = 5.0 V ± 5% T a = +25°C T a = 0°C T a = +85°C

Contextual Info: * SY10494-6/7 SY100494-6/7 SY101494-6/7 16K x 4 ECL RAM SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • Address access time, tAA: 6/7ns max. The Synergy S Y 1 0 /1 0 0 /1 0 1 4 9 4 are 65536-bit Random Access Memories RA M s , designed with advanced Emitter

Contextual Info: uIPL SYNERGY SEMICONDUCTOR PRELIMINARY TTL BICMOS STATIC RAM 64K 16KX 4-BIT V 1 FEATURES SY71B98-7 SY71B98-10 SY71B98-12 DESCRIPTION • ■ ■ ■ ■ Address access time, tA A : 7/10/12ns max. Chip select access time, tACS: 4/6/7ns max. Popular 16K x 4 with common I/O organization

Contextual Info: * SYNERGY QUAD DRIVER SY10E112 SY100E112 SEMICONDUCTOR FEATURES DESCRIPTION • 600ps max. propagation delay ■ Common enable input ■ ESD protection of 2000V ■ Fully compatible with Industry standard 10KH, 100 K I/O levels ■ Extended 100E V ee range of -4.2V to -5.46V

Contextual Info: « SYNERGY C lockw orks PRELIMINARY FREQUENCY SYNTHESIZER SY89429 SEMICONDUCTOR DESCRIPTION FEATU R ES The SY89429 is a general purpose, synthesized clock source targeting applications that require both serial and parallel interfaces. Its Internal V co will operate over a range

Contextual Info: * Clockworks PRELIMINARY SY89429A FREQUENCY SYNTHESIZER SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • 25 to 400MHz differential PECL outputs ■ ■ ■ ■ ■ ■ 10ps rms max. jitter Minimal frequency over-shoot Synthesized architecture Serial 3 wire interface

Contextual Info: * LOW-POWER HEX ECL-to-TTL TRANSLATOR SYNERGY SY100S325 SEMICONDUCTOR DESCRIPTION FEATURES The SY100S325 are hex translators for converting 100K ECL logic levels to TTL logic levels. Inputs can be used as inverting, non-inverting o r differential receivers. An

F100K

Abstract: SY100S336 SY100S336A SY100S336ADC
Contextual Info: ENHANCED 4-STAGE COUNTER/SHIFT REGISTER m v SYNERGY . Vim <N «4 S i i 00S336A S E M IC O N D U C T O R DESCRIPTION FEATURES • Max. shift frequency of 700MHz ■ Clock to Q delay max. of 110Ops ■ Sn to TC speed improved by 50% ■ Sn set-up and hold time reduced by more than 50%

F100K

Abstract: SY100S350 SY100S350DC
Contextual Info: « SYNERGY H E X D' LATCH SY100S350 S E M IC O N D U C T O R FEATURES DESCRIPTION I Max. transparent propagation delay of 900ps I Min. Master Reset and Enable pulse widths of 100ps I I e e min. of -98mA I ESD protection of 2000V I Industry standard 100K ECL levels

31T4

Contextual Info: DS3/STS-1 CLOCK fr._. RECOVERING TRANSCEIVER O V A IC P O V S Y N cH G Y PRELIMINARY INFORMATION SEMICONDUCTOR DESCRIPTION FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Single-chlp line Interface for DS3 and STS-1 Transformers optional for connection to 75ft coax

Contextual Info: * TRIPLE D FLIP-FLOP SYNERGY SY100S331 SEMICONDUCTOR FEATURES DESCRIPTION • Max. toggle frequency of 800MHz ■ Differential outputs ■ I e e min. of -80m A ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option: