T0D13 Search Results

Contextual Info: « 01/Iie n /« V LOW-POWER HEX PECL-TO-TTL TRANSLATOR SYNERGY SEMICONDUCTOR FEATURES PRELIMINARY SY100S390 DESCRIPTION The SY100S390 is a hex PECL-to-TTL translator for converting 100K logic levels to TTL logic levels. Unlike other level translators, the SY100S390 operates using only one

Contextual Info: *SYNERGY D FLIP-FLOP WITH SET AND RESET SY10EL31 SY100EL31 SEMICONDUCTOR DESCRIPTION FEATURES The SY10/100EL31 are D flip -flop s w ith set and reset. T he d e vice s are fu n c tio n a lly e q u iva le n t to th e E131 d e vice s, w ith h ig h e r p e rfo rm a n ce ca p a b ilitie s .

Contextual Info: * ULTRA-HIGH-SPEED 64-WORD x 18-BIT FIFO SYNERGY SY69168 SEMICONDUCTOR FEATURES DESCRIPTION • 10ns read and/or write cycle ■ System clock speeds to 100MHz ■ Selectable OVERFLOW and UNDERFLOW interrupts ■ EMPTY, FULL and HALF-FULL status flag outputs

Contextual Info: * QUINT EXCLUSIVE OR/NOR GATE SYNERGY SY100S307 SEMICONDUCTOR FEATURES DESCRIPTION The SY100S307 is an ultra-fast quint exclusive-OR/ NOR gate designed for use in high-performance ECL systems. A function output that is the wire-OR result of the exclusive-OR outputs is also available. The inputs

Contextual Info: *SYNERGY SY10EL52 SY100EL52 DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP SEMICONDUCTOR DESCRIPTION FEATURES The S Y 10/100E L52 are d ifferential data, differential c lo c k D flip - flo p s w ith re s e t. T h e s e d e v ic e s a re fu n ction a lly e q u iva le nt to the E452 devices, with higher

Contextual Info: * 5-WIDE 5, 4, 4, 4, 2 OA/OAI GATE SYNERGY SY100S318 SEMICONDUCTOR FEATURES DESCRIPTION The SY100S318 is an ultra-fast 5-wide 5, 4, 4, 4, 2 OR/ AND gale with both true and complementary outputs, designed for use in high-performance ECL systems. The inputs on this device have 75K£2 pull-down resistors.

Contextual Info: SYNERGY ULTRA-HIGH-SPEED 64-WORD x 18-BIT FIFO SY69167 SEMICONDUCTOR DESCRIPTION FEATURES • 5ns read or w rite cycle ■ System clock speeds to 200MHz ■ User-selectable bandwidth — one read or one write operation each clock cycle ■ Selectabe O VERFLOW and UNDERFLOW interrupts

D241 diode

Abstract: TIL 1025 block diagram of VCD PS 1025 SY100S324 SY100S324DC SY100S324FC SY100S324JC
Contextual Info: This Material Copyrighted By Its Respective Manufacturer SY100S324 SEM IC O N D U C TO R BLOCK DIAGRAM DC ELECTRICAL CHARACTERISTICS Vee = - 4 .2 V to - 5 .4 6 V un le ss o th e rw is e specified, V c c = V c c a = G N D , V t t l = -+4.5V to -+5.5V, T a = 0 °C to + 85°C

E122

Abstract: SY100E122 SY10E122 SY10E122JC r-2524
Contextual Info: * SYNERGY S E M IC O N D U C T O R SY10E122 SY100E122 9-BIT BUFFER FEATURES_ • ■ 500ps max. propagation delay ■ Extended 100E Vee range of -4.2V to -5.5V ■ Fully compatible with industry standard 10KH, 100K I/O levels

H600

Abstract: SY10H641A
Contextual Info: * SINGLE SUPPLY 1:9 PECL-TO-TTL SYNERGY Clockworks S Y 10H 641A SY100H 641A S E M IC O N D U C T O R FE A TU R E S D ES C R IPTIO N I New design - replaces SY10/100H641 The SY10/100H641A are single supply, low skew translating 1:9 clock drivers. Devices in the Synergy

HP70004A

Abstract: HP53132A OV 5642 70874B
Contextual Info: * SONET/SDH/ATM OC-3 CLOCK RECOVERING TRANSCEIVER SYNERGY SEM IC O N D UC TO R FEATURES DESCRIPTION • A complete SONET/SDH Transmitter & Receiver ■ Complies with Bellcore, CCITT and ANSI Specifications ■ Two on-chip PLLs: One for clock generation & another for clock recovery

Contextual Info: Clockworks ADVANCE INFORMATION SY10/100EL34 -2, -5-4, +8 CLOCK GENERATION CHIP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75 KD input pull-down resistors ESD protection of 2000V

Contextual Info: A LOW-POWER OCTAL ECL/TTL SYNERGY S SEMICONDUCTOR — W l IH L A I O n “ " I DESCRIPTION FEATURES • Bi-directional translation ■ ESD protection of 2000V ■ Latched outputs ■ Voltage compensated operating range: -4.2V to -5.7V ■ Fast TTL outputs

SY100E111

Abstract: SY10E111
Contextual Info: 1:9 DIFFERENTIAL CLOCK DRIVER WITH ENABLE SYNERGY S E M IC O N D U C T O R DESCRIPTION FEATURES • Low skew ■ Extended 100E V ee range of -4.2V to -5.5V ■ Guaranteed skew limits ■ Differential design ■ V bb output ■ Enable input ■ Fully compatible with industry standard 10KH, 100K

Contextual Info: 0« SY100S366 9-BIT COMPARATOR SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES The SY100S366 is an ultra -fa st 9-bit m agnitude comparator designed for use in high-performance ECL systems. The device compares the arithmetic value of two 9-bit words and indicates whether one word is greater than

Contextual Info: « SYNERGY DUAL 8-INPUT MULTIPLEXER SEMICONDUCTOR FEATURES • SY100S363 DESCRIPTION The SY100S363 is ad ua l 8-input m ultiplexer designed fo r use in new, high-perform ance ECL systems. The three Data Select inputs So, S i , S 2 determ ine the bits from each of the inputs (An, Bn) that w ill be passed on

Contextual Info: « SYNERGY C lockw orks PRELIMINARY FREQUENCY SYNTHESIZER SY89429 SEMICONDUCTOR DESCRIPTION FEATU R ES The SY89429 is a general purpose, synthesized clock source targeting applications that require both serial and parallel interfaces. Its Internal V co will operate over a range

Contextual Info: * TRIPLE 4-INPUT MULTIPLEXER WITH ENABLE SYNERGY SY100S371 SEMICONDUCTOR FEATURES • ■ Max. propagation delay of 1000ps ■ Ie e DESCRIPTION The SY100S371 is an ultra-fast triple 4-input multiplexer with true and complementary outputs designed for use in

Contextual Info: * TRIPLE DIFFERENTIAL 2:1 MULTIPLEXER SYNERGY SY10E457 SY100E457 SEMICONDUCTOR DESCRIPTION FEATURES • ■ ■ ■ ■ ■ ■ ■ Differential D and Q Vbb output for single-ended use 700ps max. propagation delay High frequency outputs Separate and common select

Contextual Info: « LOW POWER HEX TTL-to-ECL TRANSLATOR SYNERGY SY100S324 SEMICONDUCTOR FEATURES DESCRIPTION • Max. propagation delay of 1.4ns ■ I ee mln. of -70mA ■ ESO protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option: — VEE = -4.2V to -5.46V

E143

Abstract: SY100E143 SY100E143JC SY10E143 SY10E143JC
Contextual Info: «0« 9-BIT HOLD REGISTER SYNERGY SY10E143 SY100E143 S E M IC O N D U C TO R D E S C R IP T IO N FEATURES • ■ ■ ■ ■ ■ 700MHz min. operating frequency 9 bits wide lor byte-parlty applications Asynchronous Master Reset Dual clocks ESD protection of 2000V

DAD 1000

Abstract: F100K SY100S318 SY100S318DC 10D2A
Contextual Info: 5-WIDE 5 , 4 , 4 , 4 OA/OAI g a t e SYNERGY ,2 SEMICONDUCTOR m _ _ FEATURES • ■ Max. propagation delay of 800ps I e e min. of -55m A ■ ESD protection of 2000V ■ Extended supply voltage option: — V EE = -4.2V to -5.46V

E452

Abstract: SY100EL52 SY10EL52 SY10EL52ZC 21 AC E-452
Contextual Info: SY10EL52 SY100EL52 DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP SYNERGY S E M IC O N D U C T O R DESCRIPTION FEATURES The S Y 10 /1 OOEL52 are differential data, differential c lo c k D flip - flo p s w ith re s e t. T h e s e d e v ic e s a re fu n ction a lly eq u iva le nt to the E452 devices, with higher

Contextual Info: * TRIPLE D FLIP-FLOP SYNERGY SY100S331 SEMICONDUCTOR FEATURES DESCRIPTION • Max. toggle frequency of 800MHz ■ Differential outputs ■ I e e min. of -80m A ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option: