SOJ28P300 Search Results

TC5117445CSJ

Contextual Info: TO SHIBA_ TC5117445CSJ-40,-50,-60 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORD BY 4-BIT EDO HYPER PAGE DYNAMIC RAM DESCRIPTION The TC5117445CSJ is an EDO (Hyper Page) dynamic RAM organized as 4,194,304 words by 4 bits. The

high level block diagram for asynchronous FIFO

Abstract: DIP28-W-300 LH540202 LJH540202
Contextual Info: LH540202 CMOS 1024 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540202 is a FIFO First-In, First-Out memory device, based onfully-staticCMOSdual-portSRAM tech­ nology, capable of storing up to 1024 nine-bit words. It

LGA 1156 PIN OUT diagram

Abstract: QSJ-44403 LGA 1150 Socket PIN diagram LGA 1155 Socket PIN diagram IC107-26035-20-G LGA 1151 PIN diagram REFLOW lga socket 1155 IC107-3204-G TB 2929 H alternative LGA 1155 pin diagram
Contextual Info: DIP8-P-300-2.54 5 Package material Lead frame material Pin treatment Package weight g Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 0.46 TYP. 2/Dec. 11, 1996 DIP14-P-300-2.54 5 Package material Lead frame material Pin treatment Package weight (g)

Contextual Info: LH52258A CMOS 32K x 8 Static RAM When E is LOW and W is HIGH, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation, new Read cycles can be

CMOS ASYNCHRONOUS FIFO 32 PIN

Abstract: LH540202 32-PIN
Contextual Info: LH540202 CMOS 1024 x 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540202 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM technology, capable of storing up to 1024 nine-bit words. It

LH540203

Abstract: LH5498 32-PIN
Contextual Info: LH540203 CMOS 2048 x 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540203 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM technology, capable of storing up to 2048 nine-bit words. It

5Z25

Contextual Info: CMOS 32K x 8 Static RAM FEATURES • Fast Access Times: 20/25 ns • Low-Power Standby when Deselected • TTL Compatible I/O • 5 V + 10% Supply • Fully-Static Operation • JEDEC Standard Pinout • Packages: 28-Pin, 300-mil DIP 28-Pin, 300-mil SOJ FUNCTIONAL DESCRIPTION

Contextual Info: LH521002C SHARP CMOS 256K x 4 Static RAM Data Sheet FEATURES The ‘L’ version will retain data down to a supply voltage of 2 V. A significantly lower current can be obtained Idr under this Data Retention condition. CMOS Standby Current (lSB2) ¡s reduced on the ‘L’ version with respect to

Contextual Info: LH540204 CMOS 4096 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing The LH540204 is a FIFO First-In, First-Out memory

Contextual Info: LH540204 CMOS 4096 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing The LH540204 is a FIFO First-In, First-Out memory

TC5117440BSJ60

Abstract: TC5117440BSJ TC5117440BSJ/BST-70
Contextual Info: TOSHIBA TC5117440BSJ-60/70 PRELIMINARY 4,194,304 WORD X 4 BIT DYNAMIC RAM Description The TC5117440BSJ is the new generation dynamic RAM organized 4,194,304 word by 4 bits. The TC5117440BSJ utilizes Toshiba’s CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating margins,

425M

Abstract: DIP18 DIP20 DIP28 DIP32 DIP40 SOJ28-P-400-1 PGA wire bonding IPGA400-C-S33U-1 PGA240
Contextual Info: 2. 外形寸法図 2. 外形寸法図 2 2-1. パッケージ外形寸法 - 2 2-1-1. パッケージ寸法表示記号 - 2 2-1-2. リード位置許容値について - 3

Contextual Info: LH540204 CMOS 4096 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 20/25/35/50 ns The LH540204 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM tech­ nology, capable of storing up to 4096 nine-bit words. It

lh52258

Contextual Info: LH52258 / FEATURES CMOS 32K x 8 Static RAM When E is LOW and W is HIGH, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation, new Read cycles can be performed by simply changing the address.

LH52258A

Abstract: SOJ8
Contextual Info: LH52258A FEATURES • Fast Access Times: 20/25 ns • Low-Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully-Static Operation • JEDEC Standard Pinout • Packages: 28-Pin, 300-mil DIP 28-Pin, 300-mil SOJ FUNCTIONAL DESCRIPTION

Contextual Info: LH52253 FEATURES • Fast Access Times: 20/25/35 ns • Low Power Standby when Deselected • TTL Compatible I/O • 5 V ± 1 0 % Supply • Fully Static Operation • Common I/O for Low Pin Count • JEDEC Standard Pinouts • Packages: 28-Pin, 300-mil DIP

Contextual Info: PRELIMINARY LH540203 C M O S 2048 X 9 A sy n ch ro n o u s FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540203 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM tech­ nology, capable of storing up to 2048 nine-bit words. It

Contextual Info: LH540201/02 PRELIMINARY CMOS 512 x 9 /1 0 2 4 x 9 A syn ch ro n o u s FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540201/02 is a FIFO First-In, First-Out mem­ ory device, based on fully-static CMOS dual-port SRAM

32PLCC

Contextual Info: LH540202 CMOS 1024 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing

Contextual Info: TOSHIBA TC55B328P/J-10/12 SILICON GATE BiCMOS 32,768 WORD x 8 BIT BiCMOS STATIC RAM Description The TC55B328P/J is a 262,144 bit high speed BiCMOS static random access memory organized as 32,768 words by 8 bits and operated from a single 5V supply. Toshiba’s BiCMOS technology and advanced circuit design enable high speed operation.

Contextual Info: TOSHIBA TC55V328J-20/25/35 PRELIMINARY SILICON GATE CMOS 32,768 WORD x 8 BIT CMOS STATIC RAM Description TheTC55V328J is a 262,144 bit CMOS high speed static random access memory organized as 32,768 words by 8 bits and designed to operate from a single 3.3V supply. Toshiba’s advanced CMOS technology and circuit design enable high speed, low

SOJ28-P-300-1

Contextual Info: SOJ28-P-300-1.27 Mirror finish 5 パッケージ材質 リードフレーム材質 端子処理方法・材質 パッケージ質量 g 版数/改版日 エポキシ樹脂 Cu アロイ 半田メッキ (≥5µm) 0.80 TYP. 3 版/96.12.5

QSJ-50074

Abstract: QSJ-44403 QFJ28-P-S450-1 QSJ-44574 SSOP60-P-700-0 SSOP30-P-56-0 SOP8-P-250-1 QSJ52627 sop44-p-600-1.27-k QFJ20
Contextual Info: 7.包装 7. 包装 7-1. 包装形態 - 2 7-1-1. 通常包装 - 2 7-1-2. 防湿包装 - 3 7-2. 個装仕様 - 4

SOJ28-P-300-1

Abstract: MSM52258
Contextual Info: E2I0023-17-Y1 ¡ Semiconductor MSM52258 ¡ Semiconductor This version: MSM52258 Jan. 1998 Previous version: Aug. 1996 32,768-Word ¥ 8-Bit CMOS STATIC RAM DESCRIPTION The MSM52258 is a 32,768-word by 8-bit CMOS fast static RAM featuring a single 5 V power supply