LH540203 Search Results

LH540203

Abstract: LH5498 32-PIN
Contextual Info: LH540203 CMOS 2048 x 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540203 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM technology, capable of storing up to 2048 nine-bit words. It

Contextual Info: PRELIMINARY LH540203 CMOS 2048 X 9 Asynchronous FIFO FUNCTIONAL DESCRIPTION FEATURES • Fast Access Times: 15/20/25/35/50/65/80 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely

Contextual Info: PRELIMINARY LH540203 C M O S 2048 X 9 A sy n ch ro n o u s FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540203 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM tech­ nology, capable of storing up to 2048 nine-bit words. It

32-PIN

Abstract: LH540203 LH5498
Contextual Info: LH540203 CMOS 2048 x 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540203 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM technology, capable of storing up to 2048 nine-bit words. It

xmxx

Abstract: L1019 Sharp IIS 22QJ
Contextual Info: SHARP CORP S1E d • fiia cm a oDDbssM s it « srpj T - H 4- 3S PRELIMINARY LH540203 CMOS 2048 x 9 Asynchronous FIFO FUNCTIONAL DESCRIPTION FEATURES • Fast Access Times: 15/20/25/35/50/65/80 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology

LH540203

Abstract: LH5498 H-1025
Contextual Info: LH540203 CMOS 2048 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing

Contextual Info: LH540203 CMOS 2048 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540203 is a FIFO First-in, First-Out memory device, based on fully-static CMOS dual-port SRAM tech­ nology, capable of storing up to 2048 nine-bit words. It

Contextual Info: LH540203 CMOS 2048 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing

Contextual Info: PRELIMINARY LH540203 CM OS 2048 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540203 is a FIFO First-In, First-Out memory device, based on fully-static CMOS dual-port SRAM tech­ nology, capable of storing up to 2048 nine-bit words. It

fifo asynch

Contextual Info: MEMORIES FIFO Memories and Shared Port RAMs ★ Under development Type Capacity Configuration Model No. Operating frequency MHz LH540203 Deeper Asynch. 18k 2k x 9 LH540203A LH540204 36k 4k x 9 FIFO LH540204A 72k 8k x 9 LH540205 Cycle time(ns) 18 Capacity

Contextual Info: LH540203 CMOS 2048 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing

n 18k U

Abstract: 132-QFP
Contextual Info: MEMORIES FIFO Memories T ype C a p a c ity Shallow Asynch. B it c o n fig u ra tio n Model No. O p e ra tin g fre q u e n c y MHz 25 64x8 LH5481 64x9 LH5491 35 0.5k A c c e s s tim e (n s ) 15 D eeper Asynch 20 25 35 50 LH5496 4.5k 512x9 9k 1k x 9 LH540202

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

20M32

Abstract: u1520
Contextual Info: CO FIFO BUFFER MEMORY/IC MEMORY CARD ★ U n d e r d e v e lo p m e n t • FIFO BUFFER MEMORIES ♦ Features • It is applicable to communication and OA equipment, as a data buffer between systems operating at different speeds. Bit Capacity configuration

LQ070T5BG01

Abstract: LM24P20 LM162KS1 BSCR86L00 IR2C07 LM5Q31 IR3Y29B BSCU86L60 lq6bw lq6bw506
Contextual Info: INDEX 1 0 4 - 1 0 9 _ DC_ GL1PR112.69 GL3KG63. 66 GL5EG41.66 1 0 4 - n 0 5 O o c .113 DC1B1CP. 100 GL1PR135.69 GL3KG8. 66

IR3Y29B

Abstract: ir3y26a1 IR4N IR3T24N IR3C08N ir2c53 ir2c05 li3301 IR3Y08 IR2E02
Contextual Info: Index Model No. IR3T ARM710 ARM7DI ARM7DM ARM7TDMI ARM7TDMI-SPL ARM8 ARM810 CMOS CMOS CMOS CMOS F series G series J series K series ID22 series ID222XX ID223XX ID224XX ID226XX ID227XX ID229XX ID22DXX ID22FXX ID22HXX ID240 series ID240DXX ID240EXX ID240GXX

Contextual Info: MEMORIES ★Under development • FIFO M emories Capacity Conlfeuralion word* x bits 64x8 0.5k 64 x 9 4.5k 512x9 1k x 9 9k 512 x 18 2k x 9 18k 1k x 18 256 x 36 x 2 4k x 9 36k 1k x 36 72k QFJ=PLCC 8k x 9 Modal No. LH5481D/U-25 LH5481D/U-35 LH5491D/U-25 LH5491D/U-35

IR2E27A

Abstract: IR2C53 IR2E02 IR2E27 IR2E10 IR3N34 IR2E31A IR2E01 IR2C07 ir2e31
Contextual Info: lndeX Model No. ARM7D CPU Core28,32,33 ARM7DM 28,33 CMOS CMOS CMOS CMOS 76 5A A F G 44 44 44 44 ID1 series ID2 series ID3 seríes ID21K064 ID21K128 ID21K256 ID21K512 ID21M010 ID21M015 ID21M020 ID21M040 ID22K256 ID22K512 ID22M010 ID22M020 ID22M040 ID22M080

ak25

Abstract: 20U20
Contextual Info: MEMORIES FIFO Memories Caoaritv uapacny !Confi Jration «ordsxbits 64 x 8 0.5k 64 x 9 Model No. Supply current Operating Access time Cycle time fWjuancy (ns) MAX. (ns) MIN. Operating Standby (MHz) MAX. (mA) MAX. (mA) MAX. LH5481D/U-25 25 - 45 - LH5481D/U-35

Contextual Info: MEMORIES FIFO M emories ★Under developm ent Type Capacity Configuration Operating frequency MHz MAX. Model No. 25 —i 35 Access time(ns) 15 20 25 35 Package SKDIP QFJ 28 28 28 28 28 28 32 — 28 28 32 28 32 28 32 28 32 50 DIP LH5481 LH5491 j — LH5496

EPM5128LC

Abstract: EPM5128GC epm5064lc-1 EPM5128LC1 59628867809r 5962-8984106LX EPM5128GI 7C19945DMB EPM5130GC-1 5962-8867812rx
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS 5962-8753903LX 5962-8753902LX CY21L49-55C CY21L49-45C CY7C281 CY7C281A 5962-8863701LX 5962-8753902LX CY6116A-45C CY6116A-35C CY7C286 CY27H512 5962-8867003LX 5962-8867002LX CY6116A-55C CY6116A-45C

philips diode PH 33J

Abstract: UM61256FK-15 sem 2106 inverter diagram IDT7024L70GB um61256 UM61256ak sram um61256fk15 HIGH VOLTAGE ISOLATION DZ 2101 C5584 IDT74LVC1G07ADY
Contextual Info: QUICKSWITCH PRODUCTS HIGH-SPEED LOW POWER CMOS 10-BIT BUS SWITCHES QS3L384 QS3L2384 FEATURES/BENEFITS DESCRIPTION • • • • • • • • • The QS3L384 and QS3L2384 provide a set of ten high-speed CMOS TTL-compatible bus switches. The low ON resistance of the QS3L384 allows inputs to be connected to outputs without

UM61256FK-15

Abstract: YD 6409 philips diode PH 33J um61256 um61256ak-15 PZ 5805 PHILIPS UM6164 KM6264BLS-7 UM61256ak sram IDT8M624
Contextual Info: QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH QUAD 2:1 MUX/DEMUX QS3257 QS32257 FEATURES/BENEFITS DESCRIPTION • • • • • • • • The QS3257 is a high-speed CMOS LVTTL-compatible Quad 2:1 multiplexer/demultiplexer. The QS3257 is a function and pinout compatible QuickSwitch

Contextual Info: MEMORIES • FIFO Memories Capacity Configuration words x bits Model No. LH5481D/U-25 Operating frequency (MHz) MAX. 25 Access time (ns) MAX. - Cycle time (ne) MIN. - Supply current operstlng/standby (mA) MAX. Supply voltage (V) 4 5/— Package 28S K -D IP /