LH52258 Search Results

3114 sram

Contextual Info: SHARP CORP S1E D • AlflOTTA 0Q0bc!2A 70S B S R P J T -H 6 -Z 3 -I? PRELIMINARY LH52258B CMOS 32K x 8 Static RAM FEATURES FUNCTIONAL DESCRIPTION The LH52258B is a high speed 262,144 bit static RAM organized as 32K x 8. A fast, efficient design is obtained

Contextual Info: LH52258A CMOS 32K x 8 Static RAM When E is LOW and W is HIGH, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation, new Read cycles can be

Contextual Info: LH52258A FEATURES • Fast Access Times: 20/25 ns • Low Power Standby when Deselected • TTL Compatible I/O • 5 V± 10% Supply • Fully Static Operation • JEDEC Standard Pinout • Packages: 28-Pin, 300-mil DIP 28-Pin, 300-mil SOJ CMOS 32K x 8 Static RAM

lh52258

Contextual Info: LH52258 / FEATURES CMOS 32K x 8 Static RAM When E is LOW and W is HIGH, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation, new Read cycles can be performed by simply changing the address.

LH52258A

Abstract: SOJ8
Contextual Info: LH52258A FEATURES • Fast Access Times: 20/25 ns • Low-Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully-Static Operation • JEDEC Standard Pinout • Packages: 28-Pin, 300-mil DIP 28-Pin, 300-mil SOJ FUNCTIONAL DESCRIPTION

Contextual Info: PRELIMINARY LH52258B CMOS 32K x 8 Static RAM FUNCTIONAL DESCRIPTION FEATURES The LH52258B is a high speed 262,144 bit static RAM organized as 32K x 8. A fast, efficient design is obtained with a CMOS periphery and a matrix constructed with polysilicon load memory cells.

MB84256-15LL

Abstract: M5M5256AP-70L M5M5256P-12 MB84256 mb84256-12ll HP121 M5M5256AP-70 M5M5256P M5M5256P-15 MB84256-10L
Contextual Info: 2 5 6 K £ tt £ ÌA&K& rc CMOS X A TAAC max ns) TCAC max (ns) TOE nax (ns) S t a t i c ^ y '/ TOH Bin (ns) TOD nax (ns) T»P «in (ns) RAM (3 2 7 6 8 x8 ) ft '•» TDS nin (ns) ffi TDH (ns) TWD ■in (ns) TWR nax (ns) LH52258-25 SHARP 0—70 25 25

soj28p300

Abstract: LH52258A
Contextual Info: LH52258A FEATURES • Fast Access Times: 20/25 ns • Low-Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully-Static Operation • JEDEC Standard Pinout • Packages: 28-Pin, 300-mil DIP 28-Pin, 300-mil SOJ FUNCTIONAL DESCRIPTION

52258

Contextual Info: SHARP CORP S1E D m 61607=16 Q00b515 3MÔ «S R P J LH52258 FEATURES • Fast Access Times: 35/45/55 ns • Low Power Standby When Deselected • TTL Compatible I/O • 5 V± 10% Supply • Fully Static Operation • 2 V Data Retention • Packages: 28-Pin, 300-mil DIP

Contextual Info: PRELIMINARY LH52258A FEATURES CMOS 32K X 8 Static RAM When E is LOW and W is HIGH, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation, new Read

LH522

Contextual Info: LH52258A FEATURES • Fast Access Times: 20/25 ns • Low-Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully-Static Operation • JEDEC Standard Pinout • Packages: 28-Pin, 300-mil DIP 28-Pin, 300-mil SOJ FUNCTIONAL DESCRIPTION

Contextual Info: LH52258 FEATURES • Fast Access Times: 35/45/55 ns • Low Power Standby When Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • 2 V Data Retention • Packages: 28-Pin, 300-mil DIP 28-Pin, 300-mil SOJ CMOS 32K x 8 Static RAM

Contextual Info: LH52258A FEATURES • Fast Access Times: 20/25 ns • Low-Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully-Static Operation • JEDEC Standard Pinout • Packages: 28-Pin, 300-mil DIP 28-Pin, 300-mil SOJ FUNCTIONAL DESCRIPTION

km681001j-20

Abstract: TC55B328J-12 256Kx4 TC55B465J10 TC55B8128J20 PDM41028SA-15SO TC55B8128J-12 TC55328J-20 KM681001J-25 PDM41024S20
Contextual Info: Cross Reference Guide Cross Reference Guide ALLIANCE VS PARADIGM AS7C1024-10TJ AS7C1024-12TJ AS7C1024-15TJ AS7C1024-20TJ AS7C1024L-10TJ AS7C1024L-12TJ AS7C1024L-15TJ AS7C1024L-20TJ AS7C1028-10TJ AS7C1028-12TJ AS7C1028-15TJ AS7C1028-20TJ AS7C1028L-10TJ AS7C1028L-12TJ

Contextual Info: MEMORIES * S tic RAMs Process C apacity Configuration Model No. A ccess tim e ns 70 80 90 100 120 LH5116 16k Full CMOS 64k 2k X 8 8k X 8 LH5116H f- Supply voltage : 5 V * 10% QpewBng tew ^raw » : ~ 40to85'C LH5116S j- Supply voltage : 3 V ± 10% LH5164A

BNK-17

Contextual Info: MEMORIES ★Under development • S ta tic RA M s Process Capacity Configuration words X bits Modal No. 2k X 8 Full CMOS 64k 8k X 8 256k 32k X 8 64k 8k X 8 64k X 4 256k 32k X 8 64k X 8 CMOS periphery 100 40/0.001 5 ± 10% O to 70 100 40/0.001 5 ± 10% - 4 0 to 85

5Z25

Contextual Info: CMOS 32K x 8 Static RAM FEATURES • Fast Access Times: 20/25 ns • Low-Power Standby when Deselected • TTL Compatible I/O • 5 V + 10% Supply • Fully-Static Operation • JEDEC Standard Pinout • Packages: 28-Pin, 300-mil DIP 28-Pin, 300-mil SOJ FUNCTIONAL DESCRIPTION

LH5160N

Abstract: LH5115 LH5118D LH5160 LH5160D LH521000 LH5167 LH52252A LH5114H LH5911-55
Contextual Info: NOV 0 5 1990 L H 5 9 1 1 /L H 5 9 1 2 /L H 5 9 1 4 2K x 8 CMOS Dual Port RAM Preliminary Data Sheet Features Functional Description The IH 5911, LH5912 and LH5914are dual port static RAMs that use true dual port memory cells to allow each port to independently access any location in memory.

organizational structure samsung

Abstract: NMS256X8 MICRON Cross Reference NMS256 256K RAM HM62256 MK6264 51256SL TC5565 "cross reference" MN44256 M5M5256
Contextual Info: Static RAM Cross Reference STATIC RAM CROSS REFERENCE ORGANIZATIONAL STRUCTURE 2K 2K X X 32K 8K X e w/CE, OE 8 W/CE1, CE2 X 8 Stow 8 Slow COMPETITIVE VENDOR SH ARP MODEL LH5116 LH5118 LH51256 LH5164A AMD Am9128 Harris CDM6116 Hitachi HM6116A Hyundai HY6116

LH5911

Abstract: lh5167-55 LH5101 LH52250 LH5160D LH5167 LH52252 LH5114H lh5160n 4kx8 static ram ttl
Contextual Info: NOV 0 5 1990 L H 5 9 1 1 /L H 5 9 1 2 /L H 5 9 1 4 2K x 8 CMOS Dual Port RAM Preliminary Data Sheet Functional Description Features The LH5911. LH5912 and LH5914are dual port static RAMs that use true dual port memory cells to allow each port to independently access any location in memory.

mn4117405

Abstract: NN5118165 XL93LC46AP NN514265 MS6264L-10PC w24M257 NN514265A w24m257ak-15 HY62256ALP10 mhs p80c51
Contextual Info: ISSI CROSS REFERENCE GUIDE Integrated Silicon Solution, Inc. ISSI ® Integrated Silicon Solution, Inc. CROSS REFERENCE GUIDE SRAM DRAM EEPROM EPROM MICROCONTROLLER JUNE 1999 Integrated Silicon Solution, Inc. CP005-1F 6/1/99 1 ISSI CROSS REFERENCE GUIDE

UM61256AK-15

Abstract: UM61256ak sram um61256ck-20 HY62256ALP10 XL93LC46AP w24m257 GVT7164D32Q-6 km62256blg-7 w24m257ak-15 UM61256
Contextual Info: ISSI CROSS REFERENCE GUIDE Integrated Silicon Solution, Inc. ISSI ® Integrated Silicon Solution, Inc. CROSS REFERENCE GUIDE SRAM DRAM EEPROM EPROM FLASH MICROCONTROLLER SERIAL FLASH JULY 1998 Integrated Silicon Solution, Inc. CP005-1E 7/1/98 1 ISSI CROSS REFERENCE GUIDE

lh5168

Contextual Info: MEMORIES Static RAMs ★ Under development P ro ce ss C a p a c ity C o n fig u ra tio n Model No. A c c e s s tim e n s 70 80 90 100 120 LH5116 2k X 8 16k LH51116H Operating temperature : - 40 to 8 5 t IUUU "O LH5116S Supply voltage : 3 V±10% LH5168 Full

5268A

Abstract: 28-SOP LH521002AK-2S 28SOP LH52256CVN
Contextual Info: MEMORIES S tatic RAMs Process Capacity Configuation words Xbits 2k 16k 8 X Access time Supply current ns) MAX. Cycle time Operating, Standby (ns) MIN. !mA) MAX. (mA) MAX. Model No. Supply Operating voltage temp. 0C) m i i LH 5116/NA/D-10 100 40 0.001 5 ± 10%