LH521 Search Results

Contextual Info: LH521002A CMOS 256K x 4 Static RAM • Low Power Standby when Deselected High frequency design techniques should be em­ ployed to obtain the best performance from this device. Solid, low impedance power and ground planes, with high frequency decoupling capacitors, are desirable. Series

Contextual Info: LH521028 FEATURES • Fast Access Times: 17/20/25/35 ns • Wide Word 18-Bits for: - Improved Performance - Reduced Component Count - Nine-bit Byte for Parity • Transparent Address Latch • Reduced Loading on Address Bus • Low-Power Stand-by Mode when

LH521028

Abstract: LH521028A 521028-1D
Contextual Info: LH521028A A14 A13 G A15 VSS ALE VCC VSS 9 W DQ10 4 3 2 1 52 51 50 49 48 47 46 DQ8 45 DQ7 10 44 DQ6 11 43 VCC DQ11 12 42 VSS DQ12 13 41 DQ5 DQ13 14 40 DQ4 DQ14 15 39 DQ3 DQ2 VSS 16 38 VCC 17 37 VSS DQ15 18 36 VCC DQ0 A11 DQ1 34 A12 35 20 21 22 23 24 25 26 27 28 29 30 31 32 33

LH521007AK-25

Abstract: lh521007ak 32-PIN
Contextual Info: LH521007A FEATURES • Fast Access Times: 17/20/25 ns • Two Chip Enable Controls • Low-Power Standby When Deselected • TTL Compatible I/O • 5 V ±10% Supply • Fully-Static Operation • 2 V Data Retention • Package: 32-Pin, 400-mil SOJ FUNCTIONAL DESCRIPTION

Contextual Info: LH521002C SHARP CMOS 256K x 4 Static RAM Data Sheet FEATURES The ‘L’ version will retain data down to a supply voltage of 2 V. A significantly lower current can be obtained Idr under this Data Retention condition. CMOS Standby Current (lSB2) ¡s reduced on the ‘L’ version with respect to

Contextual Info: LH521028 FEATURES • Fast Access Times: 17/20/25/35 ns • Wide Word 18-Bits for: - Improved Performance - Reduced Component Count - Nine-bit Byte for Parity • Transparent Address Latch • Reduced Loading on Address Bus • Low-Power Stand-by Mode when

LH521028

Abstract: xmxxx
Contextual Info: LH521028 CMOS 64K x 18 Static RAM operations on the high and the low bytes. The Address Latches are transparent when ALE is HIGH for applica­ tions not requiring a latch , and are latched when ALE is LOW. The Address Latches and the wide word help to eliminate the need for external Addressbusbuffers and/or

Contextual Info: LH521028 CMOS 64K x 18 Static RAM FEATURES • Fast Access Times: 17/20/25/35 ns • Wide Word 18-Bits for: - Improved Performance - Reduced Component Count - Nine-bit Byte for Parity • Transparent Address Latch • Reduced Loading on Address Bus • Low-Power Stand-by Mode when

LH521008

Abstract: ScansU9X27
Contextual Info: LH521008 FEATURES • Fast Access Times: 20/25/35 ns • Low Power Standby when Deselected • TTL Compatible I/O • 5 V ±10% Supply • Fuliy Static Operation • 2 V Data Retention • JEDEC Standard Pinout • Packages: 32-Pin, 400-mil DIP 32-Pin, 400-mil SOJ

Contextual Info: SHARP CORP blE D • filflDTTfi OOO^flfi Mbb * S R P J LH521002 FEATURES • Fast Access Times: 20/25/35 ns • JEDEC Standard Pinouts • Low Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • Common I/O for Low Pin Count

LH521002AK25

Contextual Info: LH521002A CMOS 256K x 4 Static RAM • Low Power Standby when Deselected High frequency design techniques should be employed to obtain the best performance from this device. Solid, low impedance power and ground planes, with high frequency decoupling capacitors, are desirable. Series

32-PIN

Contextual Info: LH521007B FEATURES • Fast Access Times: 17/20/25/35 ns • Two Chip Enable Controls • Low Power Standby When Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • 2 V Data Retention L Version • Packages: 32-Pin, 300-mil SOJ (Preliminary)

LH521028U-25

Abstract: LH521028
Contextual Info: LH521028 FEATURES • Fast Access Times: 17/20/25/35 ns • Wide Word 18-Bits for: – Improved Performance – Reduced Component Count – Nine-bit Byte for Parity • Transparent Address Latch • Reduced Loading on Address Bus • Low-Power Stand-by Mode when

S21002

Contextual Info: LH521002 FEATURES • Fast Access Times: 20 725/35 ns • High Density 28-Pin, 400-mil SOJ • JEDEC Standard Pinouts • Low Power Standby when Deselected • TTL Compatible I/O • 5 V± 10% Supply • Fully Static Operation • Common I/O for Low Pin Count

Contextual Info: SHARP LH521002C CMOS 256K x 4 Static RAM Data Sheet The ‘L’ version will retain data down to a supply voltage of 2 V. A significantly lower current can be obtained Idr under this Data Retention condition. CMOS Standby Current (lSB2) is reduced on the ‘L’ version with respect to

Contextual Info: LH521008 FEATURES • Fast Access Times: 20/25/35 ns • Low-Power Standby when Deselected • TTL Compatible I/O C M O S 128K x 8 Static RAM When E is LOW and W is HIGH, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs.

Contextual Info: LH521028 FEATURES • Fast Access Times: 20/25/35 ns • Wide Word 18-Bits for: - Improved Performance - Reduced Component Count - Nine-bit Byte for Parity Transparent Address Latch • Reduced Loading on Address Bus • Low Power Stand-by Mode when Deselected

lh521007

Contextual Info: PRELIMINARY LH521007/ FEATURES • Fast Access Times: 20 725/35 ns • Two Chip Enable Controls • High Density 32-Pin, 400-mil SOJ • Low Power Standby When Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • 2 V Data Retention

LH521028

Abstract: LH521028A
Contextual Info: LH521028A ALE 1 52 51 50 49 48 47 46 A14 2 A13 3 G 4 A15 VSS 5 W 6 DQ8 45 DQ7 10 44 DQ6 11 43 VCC DQ11 12 42 VSS DQ12 13 41 DQ5 DQ13 14 40 DQ4 DQ14 15 39 DQ3 DQ2 DQ10 9 VCC VSS 18 36 VCC DQ16 19 35 DQ1 DQ17 34 20 21 22 23 24 25 26 27 28 29 30 31 32 33 DQ0

DIP32-P-400

Contextual Info: PRELIMINARY LH521007 FEATURES • Fast Access Times: 20/25/35 ns • Two Chip Enable Controls • Low Power Standby When Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • 2 V Data Retention • Packages: 32-Pin, 400-mil DIP

SOJ28-P-400

Contextual Info: LH521002C CMOS 256K x 4 Static RAM Data Sheet The ‘L’ version will retain data down to a supply voltage of 2 V. A significantly lower current can be obtained IDR under this Data Retention condition. CMOS Standby Current (ISB2) is reduced on the ‘L’ version with respect to

Contextual Info: SHARP LH521007C CMOS 128K x 8 Static RAM Data Sheet When both Chip Enables are active and W is inactive, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation,

32-PIN

Abstract: SOJ32-P-300
Contextual Info: LH521007C CMOS 128K x 8 Static RAM Data Sheet When both Chip Enables are active and W is inactive, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation,

LH5s

Contextual Info: LH521008 FEATURES CMOS 128K x 8 Static RAM When E is LOW and W is HIGH, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation, new Read cycles can be performed by simply changing the address.