LH52253 Search Results

Contextual Info: LH52253 FEATURES • Fast Access Times: 17/20/25/35 ns • Low-Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully-Static Operation CMOS 64K X 4 Static RAM The LH52253 offers an Output Enable G for use in managing the Data Bus. Bus contention jluring Write

Contextual Info: LH52253 FEATURES • Fast Access Times: 20/25/35 ns • Low Power Standby when Deselected • TTL Compatible I/O • 5 V ± 1 0 % Supply • Fully Static Operation • Common I/O for Low Pin Count • JEDEC Standard Pinouts • Packages: 28-Pin, 300-mil DIP

Contextual Info: LH52253 FEATURES • Fast Access Times: 17/20/25/35 ns • Low-Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully-Static Operation • Common I/O for Low Pin Count • JEDEC Standard Pinouts • Packages: 28-Pin, 300-mil DIP

Contextual Info: SHARP E L E K / MELEC » I V 44E » b LH52253 FEATURES aiao?=ia 0004=125 ? m s r p j CMOS 32K x 8 Static RAM When E is LOW and W Is HIGH, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs.

DA72

Abstract: D-A72
Contextual Info: LH52253 FEATURES • Fast Access Times: 17/20/25/35 ns • Low-Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully-Static Operation CMOS 64K x 4 Static RAM The LH52253 offers an Output Enable G for use in managing the Data Bus. Bus contention_during Write

A10C

Abstract: LH52253K-25
Contextual Info: ~1 ^ i f LH52253 FEATURES • Fast Access Times: 15*/20/25/35 ns • Standard 28-Pin, 300-mil DIP • S]pace Saving 28-Pin, 300-mil SOJ • JEDEC Standard Pinouts • Low Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation

5225M

Abstract: SOJ28
Contextual Info: LH52253 FEATURES • Fast Access Times: 20/25/35 ns • Low-Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully-Static Operation C M O S 64K x 4 Static R A M The LH52253 offers an Output Enable G for use in managing the Data Bus. Bus contention _during Write

Contextual Info: LH52253 FEATURES • Fast Access Times: 17/20/25/35 ns • Low-Power Standby when Deselected • TTL Compatible I/O • 5 V + 10% Supply • Fully-Static Operation CMOS 64K x 4 Static RAM The LH52253 offers an Output Enable G for use in managing the Data Bus. Bus contention during Write

km681001j-20

Abstract: TC55B328J-12 256Kx4 TC55B465J10 TC55B8128J20 PDM41028SA-15SO TC55B8128J-12 TC55328J-20 KM681001J-25 PDM41024S20
Contextual Info: Cross Reference Guide Cross Reference Guide ALLIANCE VS PARADIGM AS7C1024-10TJ AS7C1024-12TJ AS7C1024-15TJ AS7C1024-20TJ AS7C1024L-10TJ AS7C1024L-12TJ AS7C1024L-15TJ AS7C1024L-20TJ AS7C1028-10TJ AS7C1028-12TJ AS7C1028-15TJ AS7C1028-20TJ AS7C1028L-10TJ AS7C1028L-12TJ

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

BNK-17

Contextual Info: MEMORIES ★Under development • S ta tic RA M s Process Capacity Configuration words X bits Modal No. 2k X 8 Full CMOS 64k 8k X 8 256k 32k X 8 64k 8k X 8 64k X 4 256k 32k X 8 64k X 8 CMOS periphery 100 40/0.001 5 ± 10% O to 70 100 40/0.001 5 ± 10% - 4 0 to 85

LH5160N

Abstract: LH5115 LH5118D LH5160 LH5160D LH521000 LH5167 LH52252A LH5114H LH5911-55
Contextual Info: NOV 0 5 1990 L H 5 9 1 1 /L H 5 9 1 2 /L H 5 9 1 4 2K x 8 CMOS Dual Port RAM Preliminary Data Sheet Features Functional Description The IH 5911, LH5912 and LH5914are dual port static RAMs that use true dual port memory cells to allow each port to independently access any location in memory.

organizational structure samsung

Abstract: NMS256X8 MICRON Cross Reference NMS256 256K RAM HM62256 MK6264 51256SL TC5565 "cross reference" MN44256 M5M5256
Contextual Info: Static RAM Cross Reference STATIC RAM CROSS REFERENCE ORGANIZATIONAL STRUCTURE 2K 2K X X 32K 8K X e w/CE, OE 8 W/CE1, CE2 X 8 Stow 8 Slow COMPETITIVE VENDOR SH ARP MODEL LH5116 LH5118 LH51256 LH5164A AMD Am9128 Harris CDM6116 Hitachi HM6116A Hyundai HY6116

LH5911

Abstract: lh5167-55 LH5101 LH52250 LH5160D LH5167 LH52252 LH5114H lh5160n 4kx8 static ram ttl
Contextual Info: NOV 0 5 1990 L H 5 9 1 1 /L H 5 9 1 2 /L H 5 9 1 4 2K x 8 CMOS Dual Port RAM Preliminary Data Sheet Functional Description Features The LH5911. LH5912 and LH5914are dual port static RAMs that use true dual port memory cells to allow each port to independently access any location in memory.

9660t

Abstract: LH521008
Contextual Info: SHARP b OE CORP D • Ô1ÔD7TÔ DDDTME? 302 «SRPJ 'T - H C - 2 3 - / O LH101504 LH101510 . R E L I M I N A Ü 3 H 1 3 C5 WF A,s Au Ai 3 R Y High-Speed BiCMOS 1M 1M xi ECL Static RAM ■ Description ■ The LH101504/LH101510 is a 256K/1M-bit high speed

LHS168

Abstract: LH52252A LH52252
Contextual Info: V .J 1 íVt! Static RAMs ★Under development Process Capacity Model No. Configuration Access time ns 70 -I 16k 2k Package 90 100 120 LH5116 J— I. 24 24 24 LH5116H 3 -T 24 24 24 - Z ÏÏ-J 1 24 24 24 C E , C S c o n tro l Data retention current : 0.2 pAjMAXj j

4108 RAM

Contextual Info: CMOS 64K x 4 Static RAM FEATURES • Fast Access Times: 15 720/25/35 ns • Standard 28-Pin, 300-mil DIP • Space Saving 28-Pin, 300-mil SOJ • JEDEC Standard Pinouts • Low Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply •

100 10L AD

Abstract: LH521007AK-25 LH5168ST LH5168SHN lh5168 LH521002AK20
Contextual Info: MEMORIES • S ta tic R A M s Process Capacity ★ U nderdevelopm ent Configuration words Xbits Model No. Access tim e Supply current (ns) MAX. Cycle time operating/standby ImA) MAX. (ns) MIN. Supply voltage (V) Operating temperature (1C) Package LH5116/NA/D-10