Q13L Search Results

70P3337

Abstract: 70P3307
Contextual Info: PRELIMINARY DATASHEET IDT70P3307 IDT70P3337 1024K/512K x18 SYNCHRONOUS DUAL QDR-IITM Features ◆ 18Mb Density 1024K x 18 – Also available 9Mb Density (512K x 18) QDR-II x 18 Burst-of-2 Interface – Commercial: 233MHz, 250MHz Separate, Independent Read and Write Data Ports

TAA 611 T12

Abstract: x48 chipset IDT72T6360 IDT72T6480 D25N3
Contextual Info: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM FEATURES • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag

s 15018

Contextual Info: N T E ELECTRONIC?; TNC_ ¿ s e ]> • b 4 3 1 5 S ci 0 0 0 5 7 0 3 2bb H N T E T -S # 'O l POSITIVE, 3 TERMINAL, ARRANGED BY OUTPUT VOLTAGE Vottag* n Regulated Voltage Out ±5% Volti) KTEfype Number Cm * Styl« (Vo«*) Diagram Number V«ui V* Hu urn

Contextual Info: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 36 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM FEATURES • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag

Contextual Info: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag

TAA 611 T12

Abstract: 72T6480 BA1-B11 d25n3 BA0-C11 k4h561638f A11-C10 q35t Q35T1 A7D9
Contextual Info: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag

Contextual Info: [ p fô iiy o » « ? in t e i M82380 HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS High Performance 32-Bit DMA Controller — 40 Mbytes/sec Maximum Data Transfer Rate at 20 MHz — 8 Independently Programmable Channels

Contextual Info: SONY CXD2409R Timing Controller for ICX076/077AL Description The CXD2409R is a timing controller for CCD camera systems which use the ICX076/077AL black-and-white CCD image sensors. Features • Supports EIA/CCIR standards • Electronic iris electronic shutter function

Q13L

Abstract: 70P3337 CQX 89 IDT70P3307 IDT70P3337 diode d5r 70P3307
Contextual Info: PRELIMINARY DATASHEET IDT70P3307 IDT70P3337 1024K/512K x18 SYNCHRONOUS DUAL QDR-IITM Features ◆ 18Mb Density 1024K x 18 – Also available 9Mb Density (512K x 18) QDR-II x 18 Burst-of-2 Interface – Commercial: 233MHz, 250MHz Separate, Independent Read and Write Data Ports

72T6480

Abstract: dsc-6358 IDT72T6360 IDT72T6480 D2312
Contextual Info: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM FEATURES • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag

70P35

Abstract: 70P3517
Contextual Info: PRELIMINARY DATASHET IDT70P3537 IDT70P3517 512K/256K x36 SYNCHRONOUS DUAL QDR-IITM Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ 18Mb Density 512K x 36 – Also available 9Mb Density (256K x 36) QDR-II x 36 Burst-of-2 Interface – Commercial: 233MHz, 250MHz Two independent ports

CQX 89

Abstract: DIODE Q20L Q33R Q19L Q23R d27l doff IDT70P3537 IDT70P3517 Q13R
Contextual Info: PRELIMINARY DATASHET IDT70P3537 IDT70P3517 512K/256K x36 SYNCHRONOUS DUAL QDR-IITM Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ 18Mb Density 512K x 36 – Also available 9Mb Density (256K x 36) QDR-II x 36 Burst-of-2 Interface – Commercial: 233MHz, 250MHz Two independent ports

MSC1150

Abstract: Q18c msc1150m Q2SC MSC1150RS
Contextual Info: OKI semiconductor MSC1150 / MSC1171/ MSC1173 Under development 10-bit/20-bit/32-bit ANODE/GRID DRIVER GENERAL DESCRIPTION T h e M S C 1 1 5 0 / M S C 1 1 7 1 / M S C 1 1 7 3 a r e v a c u u m f lu o r e s c e n t d is p la y d r iv e r IC s w h ic h c o n s is t o f s h ift

IDT72T6360

Abstract: IDT72T6480 2x16Mb
Contextual Info: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 36 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag

72T63

Contextual Info: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 36 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag

72T63

Contextual Info: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 36 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag

Q11L

Abstract: 70P3337 CQX 89 IDT70P3307 IDT70P3337 RM-576 Q15L tbl17 BW1R q11r
Contextual Info: PRELIMINARY DATASHEET IDT70P3307 IDT70P3337 1024K/512K x18 SYNCHRONOUS DUAL QDR-IITM Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ 18Mb Density 1024K x 18 – Also available 9Mb Density (512K x 18) QDR-II x 18 Burst-of-2 Interface – Commercial: 233MHz, 250MHz

DIODE Q20L

Abstract: D34l IDT70P3517 Q21L CQX 89 IDT70P3537 Q20L D34R Q26R Q11L
Contextual Info: PRELIMINARY DATASHET IDT70P3537 IDT70P3517 512K/256K x36 SYNCHRONOUS DUAL QDR-IITM Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ 18Mb Density 512K x 36 – Also available 9Mb Density (256K x 36) QDR-II x 36 Burst-of-2 Interface – Commercial: 233MHz, 250MHz Two independent ports

DQS7-G17

Abstract: BA1-B11 IDT72T6360 IDT72T6480 72T6360 D10-K3 DQS5-B16
Contextual Info: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 36 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM FEATURES • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag

TAA 611 T12

Abstract: A6C9 128M DDR SDR SDRAM samsung 0 IDT72T6360 IDT72T6480
Contextual Info: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag

TAA 611 T12

Abstract: 17x18 BA0-C11 DQ51d DQ34-C12
Contextual Info: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 36 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag

Contextual Info: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM FEATURES • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag

TAA 611 T12

Abstract: IDT72T6360 IDT72T6480
Contextual Info: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 36 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM FEATURES • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag