2BL75 Search Results

82430LX

Contextual Info: in te * 82433LX/82433NX LOCAL BUS ACCELERATOR LBX Supports th e Full 64-bit Pentium- Processor Data Bus at Frequencies up to 66 MHz (82433LX and 82433NX) Dual-Port Architecture Allows Concurrent Operations on the Host and PCI Buses Drives 3.3V Signal Levels on the CPU

Contextual Info: in te i 80C186EC/80C188EC AND 80L186EC/80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS • Fully Static Operation H True CMOS Inputs and Outputs ■ Integrated Feature Set: — Low-Power, Static, Enhanced 8086 CPU Core — Two Independent DMA Supported

Contextual Info: Ä P M Ä IM ! OM F©KffiíL&YO©M in te i 82374EB/82374SB EISA SYSTEM COMPONENT (ESC In te g ra te s E ISA C o m p a tib le Bus C o n tro lle r — T ra n s la te s C y cles B e tw e e n E ISA and ISA Bus — S u p p o rts E IS A B u rst an d S tan d ard

82489DX AP-388

Abstract: 82489dx intel 82357 intel 82489dx
Contextual Info: 82489DX ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER 82489DX FEATURES OVERVIEW • Inter-Processor Interrupts ■ Advanced Interrupt Controller for 32-Bit Operating Systems ■ Various Addressing Schemes— Broadcast, Fixed, Lowest Priority, etc. ■ Solution for Multiprocessor Interrupt

Contextual Info: 8x930HjrUNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER 1.0 ABOUT THIS DOCUMENT 1.2 This data sheet contains advance information about Intel’s 8*930Hjr Universal Serial Bus hub peripheral controller, based on the MCS 251 peripheral controller, which includes a functional overview,

Contextual Info: intJ 80C187 80-BIT MATH COPROCESSOR • High Performance 80-Bit Internal Architecture ■ Implements ANSI/IEEE Standard 7541985 for Binary Floating-Point Arithmetic ■ Upward Object-Code Compatible from 8087 ■ Fully Compatible with 387DX and 387SX Math Coprocessors. Implements all 387

Contextual Info: P fö H y K ä M Ä G W in te i 80L960JA/JF 3.3V EMBEDDED 32-BIT MICROPROCESSOR 3.3 V Version o f the 80960JA/JF Processor Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model

Contextual Info: 80960CF-40 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 71 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-Bit Burst Bus with Pipelining

hall marking code A04

Abstract: INTELDX4 write-through YSS 928
Contextual Info: INTEL486 PROCESSOR FAMILY • lntelDX4TM P ro c e s s o r — Up to 100-MHz Operation -Speed-M ultiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Cache — Integrated Floating-Point Unit — 3.3V Core Operation with 5V Tolerant I/O Buffers

D405B

Contextual Info: IN TE L CORP In i' ^ UP/PRPHLS EOE n • 4ô2 t,17S 0 0Ô 17 7 0 ô ■ I M8751H-8 “P M -S H SINGLE-COMPONENT 8-BIT MICROCOMPUTER Military ■ ■ ■ ■ ■ ■ ■ ■ Programmable Full-Duplex Serial Channel ■ 128K Accessible External Memory ■ Multiply and Divide

AS263

Abstract: 271066 l213d
Contextual Info: INTEL CORP UP/PRPHLS ' EQE |) • 4fi2bl7S OOfilSS? T ■ ¡ n y * M28F256 n?4(eHV2.7 256K (32K x 8) CMOS FLASH MEMORY M ilitary a Flash Electrical Chip-Erase ■ Command Register Architecture for Microprocessor/Microcontroller Compatible Write Interface

Contextual Info: in te i 87C196KR/KQ 87C196JV/JT 87C196JR/JQ ADVANCED 16-BIT CHMOS MICROCONTROLLER Automotive • —40°C to + 125°C Ambient ■ High Performance CHMOS 16-Bit CPU ■ High Speed Peripheral Transaction Server PTS ■ Up to 48 Kbytes of On-Chip EPROM ■ Two 16-Bit Software Timers

Bck 2801

Abstract: TB 2929 H alternative 0/TRANSFORMER bck 2801 10BASE2 10BASE5 386TM 82596DX 82596SX intel DOC 10Broad36
Contextual Info: 82596DX AND 82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting ■ Supports Industry Standard LANs — IEEE TYPE 10BASE-T (TPE),

d5017

Abstract: schematic diagram 555 PAM 82820 mch chip 8-pin H049 obd usb api 4st 03 82820 GAR7 H027 MLT 22 542
Contextual Info: intei Intel 820 Chipset: 82820 Memory Controller Hub MCH Datasheet November 1999 Order Number: 290630-001 2bl75 GEGTTlb Ö5Ö • Intef* 82820 MCH intel. Information in this docum ent is provided In connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

270646

Abstract: 87L51FC 80L51FA 83L51FA 83L51FB 83L51FC 87L51FA 87L51FB 272356-001 fx20
Contextual Info: 4 A m H ] (i O[M[F®lf3GK0AYD®N in y 8XL51 FA/FB/FC LOW VOLTAGE CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS Commercial/Express 87L51FA/83L51FA/80L51FA/87L51FB/83 L51FB/87L51FC/83L51FC High Performance CHMOS OTP ROM/ Boolean Processor ROM/CPU 32 Programmable I/O Lines

Contextual Info: P K ilL D IM in K IA IS V in te l 8XC196MD INDUSTRIAL MOTOR CONTROL MICROCONTROLLER 87C196MD 16 Kbytes of On-Chip OTPROM* 87C196MD, ROM 16 Kbytes of On-Chip Factory-Programmed OTPROM 80C196MD ROMIess High-Performance CHMOS 16-Bit CPU Programmable Frequency Generator

Contextual Info: In te l 28F512 512K 64K x 8 CMOS FLASH MEMORY Flash Electrical Chip-Erase — 1 Second Typical Chip-Erase Quick-Pulse Programming Algorithm — 10 /as Typical Byte-Program — 1 Second Chip-Program 100,000 Erase/Program Cycles 12.0V ± 5 % Vpp High-Performance Read

gi 9644 diode

Abstract: INTELDX4 write-through
Contextual Info: in te i, MILITARY Intel 486 PROCESSOR FAMILY • Write-Back Enhanced ln t e l D X 4 ™ Processor — Up to 100-MHz Operation -Speed-M ultiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Write-Back Cache — Integrated Floating-Point Unit

Contextual Info: ¡n tj 82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Com plete C SM A/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting — HDLC Frame Delimiting ■ Supports Industry Standard LANs

Contextual Info: in t e i A O W A t M ! D M F @ I^ ß iflÄ ¥ D fiO 28F008SA-L 8-MBIT (1 MBIT x 8 FLASH FI LETM MEMORY • High-Density Symmetrically-Blocked Architecture — Sixteen 64-Kbyte Blocks ■ Low-Voltage Operation 3.3V + 0.3V or 5.0V ±10% Vcc ■ Extended Cycling Capability

diodo sl r7

Abstract: TMs 1122 NL BC 1305 pin outs DIODO 6N c11 cpl 100 39p HBT 01 - 04G Intel486TM PROCESSOR FAMILY 6M91 INTEL I486 DX2 diodo s4 6n
Contextual Info: intei MILITARY ln t e l 486 TM PROCESSOR FAMILY • lntelDX4TM Processor — Up to 100-MHz Operation -S peed-M ultiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Cache — Integrated Floating-Point Unit — 3.3V Core Operation with 5V Tolerant

ma6351

Abstract: LE-24T ZO 607MA A82496 290446 EM 5135 diode 522110 jp 486TM 241429 dm4021
Contextual Info: INTEL CORP -CUP/PRPHLSJ S7E D • 4 fl2 bl 7 5 01522147 t»23 ■ in te l Pentium Processor User's Manual Volume 2: 82496 Cache Controller and 82491 Cache SRAM Data Book NOTE: The Pentium™ Processor User's Manual consists of three books: Pentium™ Processor Data Book, Order Number 241428; the

APIC D06

Abstract: intel core i7 P64H ir020 T40 NO3 82806AA M66EN PAR64 REQ64 intel81
Contextual Info: i n t J Intel 82806AA PCI 64 Hub P64H Datasheet November 1999 Order Number: 298025-001 4fl5bl7S G E l O m t 427 • Inte!9 82806AA PCI 64 Hub (P64H) Information in this docum ent is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

A4232-01

Abstract: 80C251 wsa0 microcontroller intel 8293 Scans-00122849
Contextual Info: [F[^@[D y T iP^i^OiW in te i 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER • Complete Universal Serial Bus Specification compatibility — Supports Isochronous and Non-isochronous data I Power-saving Idle and Powerdown Modes I User-selectable Configurations