402BL Search Results

80C452-1

Abstract: DIA DB3
Contextual Info: ’r INTEL CORP UP/PRPHLS intgl 31E D ~ ' - -r.-' • 402bli7S OQfl'ifim 5 ■ 9 r - ? 2 - 3 Z - ir UPI-452 CHMOS PROGRAMMABLE I/O PROCESSOR 83C452 - 8K x 8 Mask Programmable Internal ROM 80C452-External ROM/EPROM 83C452/80C452:3.5 to 14 MHz Clock Rate Software Compatible with the MCS-51

80188

Abstract: intel 80188
Contextual Info: INTEL CORP UP/PRPHLS m 44E D 402bl7S D'lDSB?*! 7 B I T L 1 T 'Y ? '/ 7 '0 7 80188 HIGH INTEGRATION 8-BIT MICROPROCESSOR Integrated Feature Set — Enhanced 8086-2 CPU — Clock Generator — 2 Independent DMA Channels — Programmable Interrupt Controller'

Contextual Info: in te l 28F020 2048K 256K x 8 CMOS FLASH MEMORY Flash Electrical Chip-Erase — 2 Second Typical Chip-Erase Quick-Pulse Programming Algorithm — 10 jas Typical Byte-Program — 4 Second Chip-Program 100,000 Erase/Program Cycles 12.0V ± 5 % Vpp High-Performance Read

Contextual Info: P W iy iM D K M W in tJ . 87C51/80C51BH/80C31BH CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial/Express 87C51/80C51BH/80C51BHP/80C31BH "See Table 1 for Proliferation Options High Performance CHMOS EPROM 5 Interrupt Sources 24 MHz Operation Programmable Serial Port

Contextual Info: ^ EXUKDTT [PIRilMlG inte* 87C196KT/87C196KS 20 MHz ADVANCED 16-BIT CHMOS MICROCONTROLLER Automotive —40°C to + 125°C Ambient High Performance CHMOS 16-Bit CPU Up to 32 Kbytes of On-Chip EPROM Up to 1 Kbyte of On-Chip Register RAM Up to 512 Bytes of Additional RAM

Contextual Info: I P ^ iU ö Ä Ä f in te i 28F008SA 8-MBIT 1-MBIT x 8 F la s h F ile T M MEMORY Extended Temperature Specifications Included High-Density Symmetrically Blocked Architecture — Sixteen 64-Kbyte Blocks Very High-Performance Read — 85 ns Maximum Access Time

Contextual Info: Ä M Ä K I I 0 M F @ [^ O ii]Ä ¥ 0 ® M VS28F016XS, MS28F016XS 16-MBIT 1 MBIT x 16, 2 MBIT x 8 SYNCHRONOUS FLASH MEMORY • VS28F016XS 40°C to +125°C — QML Certified — SE2 Grade ■ 0.25 MB/sec Write Transfer Rate ■ MS28F016XS 55°C to 125°C

Contextual Info: intJ. 2-MBIT 128K x 16, 256K x 8 LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY 28F200BL-T/B, 28F002BL-T/B m Low Voltage Operation for Very Low Power Portable Applications — Vcc = 3.0V-3.6 V • Automatic Power Savings Feature — 0.8 mA Typical Ice Active Current in

Contextual Info: in tj, 8XC196KC/8XC196KC20 COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER 87C196KC—16 Kbytes of On-Chip OTPROM 83C196KC—16 Kbytes ROM 80C196KC—ROMIess • 16 and 20 MHz Available ■ Dynamically Configurable 8-Bit or 16-Bit Buswidth ■ 488 Byte Register RAM

Contextual Info: intJ 82078 64 PIN CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER — Selectable Boot Drive — Standard IBM and ISO Format Features — Format with Write Command for High Performance in Mass Floppy Duplication • Small Footprint and Low Height Packages ■ Supports Standard 5.0V as well as Low

Contextual Info: 80960RP 1.0 1.2 ABOUT THIS DOCUMENT Terminology In this document, the following terms are used: This data sheet contains ADVANCE INFORMATION about Intel’s i960 RP processor, including a func­ tional overview, mechanical data package signal locations and simulated thermal characteristics ,

51FFH

Contextual Info: in te i 82092AA PCI TO PCMCIA/ENHANCED-IDE CONTROLLER • Provides the Ultimate Plug and Play Solution fo r High Perform ance PCI Desktop Systems — Supports Combinations of PCMCIA and Enhanced Local Bus IDE Interfaces — Contains a 32-bit PCI Local Bus

Contextual Info: [PIM2>[E U T P^E^OO in te i 80960HA/HD/HT 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Binary Compatible with Other80960 Processors • Two Instructions/Clock Sustained Execution 32-Bit Parallel Architecture — Load/Store Architecture — Sixteen 32-Bit Global Registers

Contextual Info: A B W A N O B O N IP O R Q W O Q N in te i 82091AA ADVANCED INTEGRATED PERIPHERAL AIP • Single-Chip PC Compatible I/O Solution for Notebook and Desktop Platforms: — 82078 Floppy Disk Controller Core — Two 16550 Compatible UARTs — One Multi-Function Parallel Port

Contextual Info: in te i 80C186EC/80C188EC AND 80L186EC/80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS • Fully Static Operation H True CMOS Inputs and Outputs ■ Integrated Feature Set: — Low-Power, Static, Enhanced 8086 CPU Core — Two Independent DMA Supported

Contextual Info: P R is y iif iiO K iÆ in r in ie l VE28F008 8 MBIT (1 MBIT x 8 FLASH MEMORY • High-Density Symmetrically Blocked Architecture — Sixteen 64 Kbyte Blocks Very High-Performance Read — 95 ns Maximum Access Time ■ Avionics Temperature Range 40°C to + 125°C

Contextual Info: 87C196CA/87C196CB 20 MHz ADVANCED 16-BIT CHMOS MICROCONTROLLER WITH INTEGRATED CAN 2.0 Automotive m High Performance CHMOS 16-Bit CPU • Full Duplex Synchronous Serial I/O Port SSIO (up to 20 MHz Operation) ■ Register-Register Architecture ■ Up to 56 Kbytes of On-Chip EPROM

132-Lead

Abstract: AD30/ako 451 960
Contextual Info: A E W Â N l ! DKIIF ß}[ü iflA 70® ß !0 in te l 80960J A /JF EMBEDDED 32-BIT MICROPROCESSOR High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers

JHTX

Contextual Info: EL CORP U P/ PR PH LS MME D a MÛ2b l 7S 0103ÔS3 S • I T L l m . . à m m s m - - 87C51FC/83C51FC 'TvHcH cVOl CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER 32 KBYTES USER PROGRAMMABLE EPROM 87C51FC/83C51FC— 3.5 MHz to 12 MHz, Vcc = 5 V ± 2 0 % 87C51FC/83C51FC-1— 3.5 MHz to 16M HZ,VCC = 5 V ± 2 0 %

Contextual Info: Intel386 EX EMBEDDED MICROPROCESSOR 1.0 INTRODUCTION The Intel386™ EXTB embedded processor operates at 20 or 25 MHz at 3 Volts nominal. The Intel386 EXTC embedded processor operates at 25 or 33 MHz at 5 Volts. In this datasheet, “Intel386 EX processor” refers to

Contextual Info: intei 28F016SV 16-MBIT 1 MBIT x 16, 2 MBIT x 8 FlashFileTM MEMORY Sm artVoltage Technology — User-Selectable 3.3V or 5V V cc -U s e r-S e le c ta b le 5V or 12V Vpp 65 ns Access Time 1 Million Erase Cycles per Block 30.8 M B /sec Burst W rite Transfer Rate

Contextual Info: A28F010 1024K 128K x 8 CMOS FLASH MEMORY (Automotive) a Extended Automotive Temperature Range: -40°C to + 125°C • Flash Memory Electrical Chip-Erase — 1 Second Typical Chip-Erase ■ Integrated Program/Erase Stop Timer B command Register Architecture for

Contextual Info: 8x930HjrUNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER 1.0 ABOUT THIS DOCUMENT 1.2 This data sheet contains advance information about Intel’s 8*930Hjr Universal Serial Bus hub peripheral controller, based on the MCS 251 peripheral controller, which includes a functional overview,

008 cow 734

Contextual Info: 80960CF-33, -25, -16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 3'2-bit Burst Bus with Pipelining