PCI INTERFACE MASTER PROGRAM Search Results

Contextual Info: PCI 9060SD MAY 1996 VERSION 0.6 PCI Bus Master Interface Chip for Master and Slave Adapters General Description _ Featu res_ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and slave adapters

ST P239

Abstract: 714 p180 verilog code for pci express memory transaction P181 Japan P135 equivalent 714 p181 XC000E HQ240 XC4013EPQ160 XC4013
Contextual Info: PCI Master Interface, PCI Slave Interface February, 1997 Product Description Features • Fully 2.1 PCI compliant 32 bit, 33MHz PCI Interface ◊ Master Initiator/Target , LC-DI-PCIM-C ◊ Slave (Target-only), LC-DI-PCIS-C PCI Master and Slave Interfaces V1.1.0

Contextual Info: PCI 9060SD T E C H N □ L □ EY November 1995 PRELIMINARY VERSION 0.5 PCI Bus Master Interface Chip for Master and Slave Adapters General Description_ Featu res_ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and

6SS4

Abstract: LA 7681 LA01 9060SD I960CX PCI9060SD Pgti
Contextual Info: T E C H N D L U PCI 9060SD E Y A November 1995 PRELIMINARY VERSION 0.5 PCI Bus Master Interface Chip for Master and Slave Adapters General Description_ Featu res_ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and

iso 4903

Abstract: 9060SD I960CX PCI9060SD
Contextual Info: PCI 9060SD T E C H N D L Q B Y MAY 1996 VERSION 0.6 PCI Bus Master Interface Chip for Master and Slave Adapters Feat u res_ General Description _ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and

MPC860

Contextual Info: PCI 9054 PCI Bus Master I/O Accelerator Chip Highlights • PCI v2.2 compliant 32-bit 33MHz Bus Master Interface Controller enables PCI Burst Transfers up to 132Mbytes/second ■ General Purpose Bus Master Interface featuring an advanced Data Pipe Architecture which

MPC860

Contextual Info: PCI 9054 PCI Bus Master I/O Accelerator Chip Highlights • PCI v2.2 compliant 32-bit 33MHz Bus Master Interface Controller enables PCI Burst Transfers up to 132Mbytes/second ■ General Purpose Bus Master Interface featuring an advanced Data Pipe Architecture which

AV96JA0330420

Abstract: V350EPC V350EPC-33LPA1 V350EPC-40LPA1 V380SDC V96BMC V96SSC PCI bridge
Contextual Info: V350EPC ENHANCED PCI BRIDGE CONTROLLER For 32-bit Multiplexed Address/Data Bus Fully compliant with PCI Local Bus Specification, Revision 2.1 Configurable for system master, PCI master, or PCI target operation 32-bit, 33 MHz PCI bus interface Direct interface to Intel i960®

V360EPC-50LPA1

Abstract: v360epc-50lp V360EPC-33LP 29030 V360EPC V360EPC-33LPA1 V380SDC V96BMC V96SSC SPACE BRIDGE SEMICONDUCTOR
Contextual Info: V360EPC ENHANCED PCI BRIDGE CONTROLLER For 32-bit De-Multiplexed Address/Data Bus Fully compliant with PCI Local Bus Specification, Revision 2.1 Configurable for system master, PCI master, or PCI target operation 32-bit, 33 MHz PCI bus interface Direct interface to Intel i960®

Contextual Info: PCI 9060 * E PCI Bus Master Interface Chip for Adapters and Embedded Systems December, 1995 VERSION 1.2 Features General Description_ • PCI Bus Master Interface supporting adapters and embedded systems • Two independent DMA channels for local bus

MPC860

Abstract: PCI9054
Contextual Info: PCI 9054 Highlights • PCI v2.2 compliant 32-bit 33MHz Bus Master Interface Controller enables PCI Burst Transfers up to 132Mbytes/second ■ General Purpose Bus Master Interface featuring an advanced Data Pipe Architecture which includes two DMA engines, programmable Target and Initiator

PCI9060SD

Abstract: doorbell application 9060SD I960CX i960 Cx Processor
Contextual Info: PCI 9060SD MAY 1996 PCI Bus Master Interface Chip for VERSION 0.6 Master and Slave Adapters _ _ _ Features_ • • • • • • • • • PCI Specification 2.1 compliant

doorbell application

Abstract: 9060SD I960CX PCI9060SD
Contextual Info: PCI 9060SD MAY 1996 PCI Bus Master Interface Chip for VERSION 0.6 Master and Slave Adapters _ _ _ Features_ • • • • • • • • • PCI Specification 2.1 compliant

9060ES

Abstract: PCI9060ES PCI9060SD small endian AD-1508
Contextual Info: PCI 9060ES November 1995 PCI Bus Master Interface Chip for VERSION 1.0 Adapters and Embedded Systems Features_ • • • • PCI Bus Master and Bus Slave transfers up to 132

doorbell application

Abstract: la2 d2 timer PIN CONFIGURATION pci 32 bit 5 v PCI9060ES PCI9060SD 10B5 9060ES 93CS56 NM93CS46
Contextual Info: PCI 9060ES November 1995 PCI Bus Master Interface Chip for VERSION 1.0 Adapters and Embedded Systems Features_ • • • • PCI Bus Master and Bus Slave transfers up to 132

V363EPC

Abstract: V363EPC-50LPA0 29030 V380SDC V96BMC V96SSC
Contextual Info: V363EPC ENHANCED PCI BRIDGE CONTROLLER For 32-bit Multiplexed/Demultiplexed Address/Data Bus Fully compliant with PCI Local Bus Specification, Revision 2.1 Configurable for system master, PCI master, or PCI target operation 32-bit, 33 MHz PCI bus interface

LA3101

Abstract: PC19060 Igus LD-310 LDL8 pci9080 80960Cx 93C06 I960CX NM93CS06
Contextual Info: PCI 9060 T E C December, 1995 VERSION 1.2 PCI Bus Master Interface Chip for Adapters and Embedded Systems Features General D escrip tio n _ • PCI Bus Master Interface supporting adapters and embedded systems • Two independent DMA channels for local

Contextual Info: LogiCORE "PCI Master and Slave interface" License Agreement Send to: Per Holmberg, Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, Fax: +1 408 879 4780 PLEASE READ THIS DOCUMENT CAREFULLY BEFORE USING THE XILINX LOGICORE PCI MASTER INTERFACE OR PCI SLAVE INTERFACE DESIGN. BY USING THE XILINX

Contextual Info: PCI 9060ES j e cT T T T S T T ^T T November 1995 VERSION 1.0 PCI Bus Master Interface Chip for Adapters and Embedded Systems Features General Description PCI Bus Master and Bus Slave transfers up to 132 megabytes/sec supporting three architectures: - PCI Direct Master adapter

PIN CONFIGURATION pci 32 bit 5 v

Abstract: 9060ES 9060SD RC32364 RC5000 pci 32 bit 5 v
Contextual Info: Support Components PLX Technology Inc. PCI 9080 I2O Compatible PCI Bus Master I/O Accelerator Chip Features Description ◆ PCI Version 2.1 compliant Bus Master interface chip for adapters and embedded systems ◆ Programmable local bus supports nonmultiplexed 32-bit

93CS56

Abstract: doorbell ID l960 pci9080 9060ES 93C06 NM93CS06 NM93CS46 PCI9060ES doorbell
Contextual Info: PCI 9060ES T e c T T T T S T T ^ T T November 1995 VERSION 1.0 PCI Bus Master Interface Chip for Adapters and Embedded Systems Features General Description PCI Bus Master and Bus Slave transfers up to 132 megabytes/sec supporting three architectures: - PCI Direct Master adapter

430fx

Abstract: Enabler iiG 82371 piix3 intel 430FX intel 80x86
Contextual Info: 82371FB PIIX AND 82371 SB (PIIX3) PCI ISA IDE XCELERATOR • Bridge Between the PCI Bus and ISA Bus ■ PCI and ISA Master/Slave Interface — PCI from 25-33 MHz — ISA from 7.5-8.33 MHz — 5 ISA Slots ■ Fast IDE Interface — Supports PIO and Bus Master IDE

9060ES

Abstract: 9060SD MPC860
Contextual Info: PCI 9080 I2O Compatible PCI Bus Master I/O Accelerator Chip Features • PCI Version 2.1 compliant Bus Master interface chip for adapters and embedded systems ■ Programmable local bus supports nonmultiplexed 32-bit address/data, multiplexed 32- or 16-bit, and

9060ES

Abstract: 9060SD MPC860 9985K
Contextual Info: PCI 9080 I2O Compatible PCI Bus Master I/O Accelerator Chip Features • PCI Version 2.1 compliant Bus Master interface chip for adapters and embedded systems ■ Programmable local bus supports nonmultiplexed 32-bit address/data, multiplexed 32- or 16-bit, and