MACRO Search Results

62A17

Abstract: HCA62A17 62A50 18PDIP 68-LCC
Contextual Info: í Order this data sheet by HCA62A00/D M MOTOROLA HCA62A00 Series SEM ICO NDUCTO RS P.O B O X 20912 • PHOENIX, A R IZ O N A 85036 HCA62A00 SERIES CMOS MACROCELL ARRAYS The HCA62A00 series m acrocell arrays are im plem ented in sil­ icon gate, 2-m icron draw n gate length, dual-layer metal intercon­

Contextual Info: MAX3785 Output Model 6.25Gbps 1.8V Board Equalizer SPICE I/O Macromodels aid in understanding signal integrity issues in electronic systems. Most of Maxim’s High Frequency/Fiber Communication ICs utilize input and output I/O circuits with Current Mode Logic (CML), Positive Emitter Coupled Logic

NET0260

Abstract: 3845 n equivalent VALUE IC net219 LTspice eldo TSH300
Contextual Info: Development of the Analog Macromodel for TSH300, ultra low-noise high-speed operational amplifier Angelo Marotta angelo.marotta@st.com STMicroelectronics May 2011 Abstract An unified analog macromodel, for Spice-like simulators, was implemented for TSH300 operational amplifier matching the real DC, Transient and AC behavior

NMTC-S40200XFYHSAY

Abstract: Character characters KS0066 KS0066U
Contextual Info: Microtips Technology Inc. 台北縣汐止鎮康寧街169巷31號12樓 Microtips Technology 12F, No 31, Lane 169, Kang Ning St. Hsi-Chih, Taipei Hsien, Taiwan, R.O.C. WEB : http://www.microtips.com.tw E-mail : Macros@microtips.com.tw TEL: 886-2-2695-3133 FAX :886-2-2695-8625

cypress flash 370

Abstract: logic block diagram of cypress flash 370 device 22v10 CY7C375 FLASH370 o112i cypress flash 370 CPLD cypress flash 370 device technology
Contextual Info: fax id: 6130 For new designs see CY7C375i CY7C375 UltraLogic 128-Macrocell Flash CPLD Features Functional Description • 28 macrocells in eight logic blocks • 28 I/O pins • 6 dedicated inputs including 4 clock pins • Bus Hold capabilities on all I/Os and dedicated inputs

ATV2500BQ

Abstract: ATV2500B ATV2500BL ATV2500BQL
Contextual Info: Features • High Performance, High Density Programmable Logic Device – Typical 7 ns Pin-to-Pin Delay – Fully Connected Logic Array With 416 Product Terms • Flexible Output Macrocell – 48 Flip-Flops - Two per Macrocell – 72 Sum Terms – All Flip-Flops, I/O Pins Feed In Independently

XC9572

Abstract: XC9572-10PC44C xc9572-15PQ100 15PC44I xc9572 data sheet XC9572-7PC44C PC44 PC84 xc9572-10pq100c XC9572-15PC84C
Contextual Info: XC9572 In-System Programmable CPLD R DS065 v4.2 April 15, 2005 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable

7C344-25

Abstract: C344 74HC CY7C344 Signal Path Designer C3445
Contextual Info: CY7C344 32-Macrocell MAX EPLD Features tional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the

XCR3128XL-10VQ100I

Abstract: XCR3128XL-10TQ144I XCR3128XL-7CS144I XCR3128XL XCR3128XL-10CS144I XCR3128XL-10VQ100C CS144 marking E13 diode L12M1 k3296
Contextual Info: R XCR3128XL 128 Macrocell CPLD DS016 v2.1 August 21, 2003 14 Preliminary Product Specification Features Description • Low power 3.3V 128 macrocell CPLD • 6.0 ns pin-to-pin logic delays • System frequencies up to 175 MHz • 128 macrocells with 3,000 usable gates

PT80

Contextual Info: ispLSI 81080V Features Functional Block Diagram • SuperBIG HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 3.3V Power Supply — 60,000 PLD Gates/1080 Macrocells — 192-360 I/O Pins Supporting 3.3V/2.5V I/O — 1440 Registers — High-Speed Global and Big Fast Megablock BFM

Programmable Divider

Abstract: 20MHZ 400M AL2007LA STD90 embedded PLL divider
Contextual Info: 0.35µ µm 20MHZ-170MHZ FSPLL AL2007LA GENERAL DESCRIPTION The AL2007LA is a Phase-Locked Loop PLL frequency synthesizer constructed in CMOS on single monolithic structure. The PLL macrofunctions provide frequency multiplication capabilities. The output clock frequency Fout is related to the reference input clock frequency Fin by the following equation:

MoSys

Abstract: CL018G tsmc 0.18um MoSys sram embedded BWEB M1T1HT18PZ32E C-l018 32K32 MoSys 1T sram
Contextual Info: High Speed Pipelined 1-Mbit 32Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1HT18PZ32E • High Performance 1T-SRAM Standard Macro • 200 MHz operation • 1-Clock cycle time • Pipelined read access timing • Late-late write mode timing • 32-Bit wide data buses

TPUMASMREF

Abstract: LF 324 M68300 M68HC16 SR15 X123 AU113 DSA00207913
Contextual Info: Time Processor Unit Macro Assembler TPUMASM Reference Manual This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. Motorola reserves the right to make changes without further notice to any products herein to improve reliability,

XCR5128

Abstract: MC16 XCR3128 Xilinx XCR5128 P-QFP40
Contextual Info: APPLICATION NOTE This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. R DS041 v1.4 January 19, 2001 XCR5128: 128 Macrocell CPLD 14* Product Specification Features Description • The XCR5128 CPLD (Complex Programmable Logic

EPC1213PC8

Abstract: EPC1PC8 EPC2LC20 epc2tc32 EPC4QC100 EPM7128* kit NIOS-EVALKIT-1C12 EPC1441PC8 EPC16UC88 EPM1270F256C5ES
Contextual Info: NEW! Package 100-TQFP 100-TQFP 100-TQFP 44-TQFP 44-TQFP 44-TQFP 44-TQFP 84-PLCC 100-TQFP 100-TQFP 100-TQFP 144-TQFP 100-TQFP 100-TQFP 144-TQFP * Tube CPLD’s Cont. Macro Cells Logic Elements Pin-Pin Delay (ns) I/O Pins Voltage Speed (NS) 64 64 64 64 64

MACH130-20

Abstract: MACH130 MACH230 PAL22V10 PAL26V16
Contextual Info: FINAL COM’L: -15/20 IND: -18/24 MACH130-15/20 Lattice Semiconductor High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 84 Pins 64 Outputs 64 Macrocells 64 Flip-flops; 4 clock choices 15 ns tPD Commercial 18 ns tPD Industrial 4 “PAL26V16” Blocks

Contextual Info: CY7C371i UltraLogic 32-Macrocell Flash CPLD Features signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. • • • • 32 macrocells in two logic blocks 32 I/O pins

resistor temprature detector datasheet

Abstract: Temprature controlled oscillator BW2010P ID16
Contextual Info: 25MHz ~ 250MHz FSPLL BW2010P FEB. 2000. Ver1.2.21 General Description Features The BW2010P is a Phase-Locked Loop PLL frequency synthesizer constructed in CMOS process technology. The PLL macrofunctions provide frequency multiplication capabilities.The output clock frequency, Fout, is related to the

parallel to serial conversion

Abstract: diode 1432
Contextual Info: Temic COMLIB MATRA MHS ATM Physical Layer ASIC Macro Library for 1.432 Description The ASIC Macro Library is consisting of specific macros which are supporting the ATM 1.432 Physical M edium Sublayer up to 622 MBit/s serial communication. This macro family, which is targeted

XC95144XL-10TQ144I

Abstract: XC95144XL-10TQG100C XAPP114 XAPP427 XC9500XL XC95144 XC95144XL XC95144XL-5-CS144 XC95144XL-5TQ100 xc95144xl tq144
Contextual Info: XC95144XL High Performance CPLD R DS056 v1.8 July 15, 2005 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

PAL26V12

Abstract: MACH120 MACH220 PAL22V10
Contextual Info: FINAL COM’L: -10/12/15/20 IND: -14/18/24 MACH220-10/12/15/20 Lattice Semiconductor High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 68 Pins 48 Outputs 96 Macrocells 96 Flip-flops; 4 clock choices 10 ns tPD 8 “PAL26V12” blocks with buried macrocells

20RA10

Abstract: 20RA10-15 PLDC20RA10 PLDC20RA10-15JC RA1021
Contextual Info: fax id: 6015 1P LDC20 RA10 PLDC20RA10 Reprogrammable Asynchronous CMOS Logic Device Features • • • • • • • • • — ICC max = 85 mA Military • High reliability — Proven EPROM technology Advanced-user programmable macrocell CMOS EPROM technology for reprogrammability

lf XTAL 20MHz

Abstract: XTAL 20MHz 20MHZ PLL2013X STD110
Contextual Info: 0.25µ µm 20MHz~170MHz FSPLL PLL2013X GENERAL DESCRIPTION The PLL2013X is a Phase-Locked Loop PLL frequency synthesizer constructed in CMOS on single monolithic structure. The PLL macro-functions provide frequency multiplication capabilities. The output clock frequency Fout is related to the input clock frequency Fin(XTALIN) by the following equation:

HCMOS9

Abstract: SATA310
Contextual Info: ST SATA310 Ideal for serial ATA and easily adapted to support SAS interfaces Offering high-performance, low-power, low-cost, and a modular design, the SATA310 is available as a fully characterized macro-cell for highly integrated SOC solutions, using STMicroelectronics’ advanced HCMOS9