BWEB Search Results

MoSys

Abstract: CL018G tsmc 0.18um MoSys sram embedded BWEB M1T1HT18PZ32E C-l018 32K32 MoSys 1T sram
Contextual Info: High Speed Pipelined 1-Mbit 32Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1HT18PZ32E • High Performance 1T-SRAM Standard Macro • 200 MHz operation • 1-Clock cycle time • Pipelined read access timing • Late-late write mode timing • 32-Bit wide data buses

P802

Abstract: PM3370 PM3380 PM3390 "filtering database"
Contextual Info: PM3370 PRELIMINARY DATASHEET PMC-970861 ISSUE 4 OCTAL FAST ETHERNET SWITCH PORT CONTROLLER PM3370 OCTAL 10/100 MBIT/S ETHERNET SWITCH PORT CONTROLLER REVISION ‘B’ DATASHEET PRELIMINARY ISSUE 3: JUNE 1998 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

ltsx e3

Abstract: ltsx e3 PM7329 SCR SS 3328 LTSX LTCE epd 47- 50 2LW MARKING CODE wrr AND I.610 0X00 PM7329
Contextual Info: PM7329 S/UNI-APEX-1K800 DATASHEET PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH PM7329 TM S/UNI - APEX-1k800 S/UNI-APEX-1K800 ATM/PACKET TRAFFIC MANAGER AND SWITCH DATASHEET ISSUE 2: JUNE, 2001 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Contextual Info: INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER TXC • Supports All 3V Pentium Processors ■ Dual Processor Support ■ PCI 2.1 Com pliant ■ Integrated Second-Level Cache Controller — — — — — — — — — ■ ■ — — Direct Mapped Organization

G175

Abstract: 234T0 82439HX CH340
Contextual Info: INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER TXC • ■ ■ ■ ■ Optional Error Checking and Correction (ECC) Supports All 3V Pentium Processors Dual Processor Support PCI 2.1 Compliant Integrated Second-Level Cache Controller — — — — — —

CY7C1362A

Abstract: GVT71512D18
Contextual Info: CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz

PM3380

Abstract: PM3370 PMC-970862
Contextual Info: APPLICATION NOTE PMC-981006 ISSUE 3 PM3370/PM3380 REVB/REVD PIN CHANGE PM3370 / PM3380 REV. B TO REV. D PIN CHANGES APPLICATION NOTE ISSUE 3: OCTOBER 1998 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE i APPLICATION NOTE

ltsx e3

Abstract: ltsx SCR SS 3328 ATLAS DSLAM structure wrr AND I.610 0X00 PM7326 MB 14231 package marking 3LW ON
Contextual Info: PM7326 S/UNI APEX DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH PM7326 TM S/UNI - APEX S/UNI APEX ATM/PACKET TRAFFIC MANAGER AND SWITCH DATA SHEET ISSUE 6: APRIL 2000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PPC403GC

Abstract: V360EPC 403GC ID31 LA25 V292PBC V3 Semiconductor
Contextual Info: Interfacing IBM’s PowerPC 403GC to PCI using V360EPC from V3 Semiconductor 1. Objective This application note describes the interface between PPC403GC processors from IBM and V360EPC Enhanced PCI Controller EPC from V3 Semiconductor. The V360EPC family of

vhdl code for fifo

Abstract: vhdl code mips code V320USC
Contextual Info: ,QWHUIDFLQJ WKH 0RWRUROD &ROGILUH  WR WKH 986& W W W W W W $SSOLFDWLRQ 1RWH  2EMHFWLYH This application note shows the interface of the MCF5307 Coldfire processor to the PCI bus using the V320USC Universal System Controller. Basic familiarity with these devices

mosys sram embedded

Abstract: CL018G M1T2HT18FE64E
Contextual Info: High Speed Flow-through 2-Mbit 32Kx64 Standard 1T-SRAM Embedded Memory Macro M1T2HT18FE64E • High Speed 1T-SRAM Standard Macro • 100 MHz operation • 1-Clock cycle time • Flow-through read access timing • Early write mode timing • 64-Bit wide data buses

MoSys 1T sram

Abstract: 64Kx32 CL018G M1T2HT18FE32E C-l018 "1t-sram"
Contextual Info: High Speed Flow-through 2-Mbit 64Kx32 Standard 1T-SRAM Embedded Memory Macro M1T2HT18FE32E • High Speed 1T-SRAM Standard Macro • 100 MHz operation • 1-Clock cycle time • Flow-through read access timing • Early write mode timing • 32-Bit wide data buses

16Kx32

Abstract: TSMC 0.18um CL018G M1T1HT18FE64E
Contextual Info: High Speed Flow-through 1-Mbit 16Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1HT18FE64E • High Speed 1T-SRAM Standard Macro • 100 MHz operation • 1-Clock cycle time • Flow-through read access timing • Early write mode timing • 64-Bit wide data buses

M1T1HT25FL32

Abstract: CL025G
Contextual Info: High Speed Flow-through 1-Mbit 32Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1HT25FL32 • High Speed 1T-SRAM Standard Macro • 83 MHz operation • 1-Clock cycle time • Flow-through read access timing • Late write mode timing • 32-Bit wide data buses

OAOLP2

Abstract: temperature digital display JUMO Lan M smd transistor 1p7 bti ml-2 transistor SMD 1p6 transistor DK qe smd edto 116.4 8052ah basic toba 639 270645
Contextual Info: MCS@51 MICROCONTROLLER FAMILY USER’S MANUAL ORDER NO.: 272383-002 FEBRUARY 1994 Intel Corporation makes no warrsnfy for the uee of ite products and assumes no responsibility for any ewors which may appear in this document nor does it make a commitment to update the information contained herein.

simm 30-pin 9-bit

Abstract: 1250H 128M NAND Flash Memory 2m edo dram 72-pin simms w6 SOT 23 2m 72-pin Flash simms 4Mx32 dram simm 8Mx32 8Mx32 dram simm simm 72 dram
Contextual Info: E PRELIMINARY INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER TXC Supports All 3V Pentium Processors Optional Error Checking and Correction (ECC) Dual Processor Support  Superior DRAM Data Integrity  Single Bit Error Correction, Multi-Bit Error Detection plus Nibble Failure

Contextual Info: PM7326 S/UNI APEX DATA SHEET ISSUE 8 ATM/PACKET TRAFFIC MANAGER AND SWITCH 3: 39 PM PMC-1981224 02 02 :0 PM7326 TM r, 20 S/UNI - De ce m be APEX n Tu es da y, 03 S/UNI APEX DATA SHEET ISSUE 8: SEPTEMBER 2002 Do wn lo ad ed by Pa rtM i ne rI nc of Pa rtm in

CL018G

Abstract: M1T1HT18FL32E MoSys sram embedded TSMC 0.18um Process parameters
Contextual Info: High Speed Flow-through 1-Mbit 32Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1HT18FL32E • High Speed 1T-SRAM Standard Macro • 100 MHz operation • 1-Clock cycle time • Flow-through read access timing • Late write mode timing • 32-Bit wide data buses

CL018G

Abstract: M1T1LT18FL32E
Contextual Info: Low Power Flow-through 1-Mbit 32Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1LT18FL32E • Low Power 1T-SRAM Standard Macro • 10-83 MHz operation • 1-Clock cycle time • Flow-through read access timing • Late write mode timing • 32-Bit wide data buses

tsmc 0.18um

Abstract: CL018G M1T1HT18FE32E
Contextual Info: High Speed Flow-through 1-Mbit 32Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1HT18FE32E • High Speed 1T-SRAM Standard Macro • 100 MHz operation • 1-Clock cycle time • Flow-through read access timing • Early write mode timing • 32-Bit wide data buses

sot T11 FRA

Abstract: CH341 ch365 1250H 430HX 82371SB 82430FX 82439HX AD11 AD12
Contextual Info: E n n n n Dual Processor Support Integrated Second-Level Cache Controller    Direct Mapped Organization Write-Back Cache Policy Cacheless, 256 KB, and 512 KB Pipelined Burst SRAMs Cache Hit Read/Write Cycle Timings at 3-1-1-1 Back-to-Back Read Cycles at

82485

Contextual Info: in te i 82485 SECOND LEVEL CACHE CONTROLLER FOR THE Intel486 MICROPROCESSOR High Performance — Zero Wait State Access on Cache Hit — One Clock Bursting — Two-Way Set Associative — Write Protect Attribute Per Tag — Start Memory Cycles in Parallel

PowerVR SGX530

Abstract: RX13a hamming code-error detection correction 16X104 INVERTER BOARD Asus A6 IR sensor LFN AMBA AXI dma controller designer user guide BA 8416 ROUND ROBIN ARBITRATION AND FIXED PRIORITY SCHEM transistor d 965 al
Contextual Info: Preliminary TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual Literature Number: SPRUGX8 1 March 2011 Preliminary 2 SPRUGX8 – 1 March 2011 Submit Documentation Feedback 2011, Texas Instruments Incorporated Contents . 91

altera epm7032

Abstract: M68060 MC68030 MCF5102 MPC860 V292BMC V292PBC
Contextual Info: Application Note: Introduction to interfacing the M68K, ColdFire and PowerQUICC CPUs to the PCI Bus V292PBC interface chip from V3 makes it easy! 1. Objective This application note describes how to interface 32-bit synchronous Motorola M680x0,