0X00 Search Results

NM95MS18

Contextual Info: NM95MS18 User’s Guide Register Summary Following is a list of registers implemented on NM95MS18 Plugn-Play controller. Registers located from 0x00 to 0x0F Word address are specific to NM95MS18 and are not part of registers defined by Plug-n-Play specification. NM95MS18 initializes itself

MSL260G

Abstract: MSL-260-G D0806 R0807 T0803 D0802 D0807 RDD0804 D0808 5 pin reset ic ARB
Contextual Info: Using the Intel 80960 CA with the PCI 9060 PCI evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000 0-15 Vendor ID, Allocated to PLX by PCI SIG (Read-only) (Default = 10B5)

NM95MS18

Abstract: ISA BUS structure
Contextual Info: Mohan Prasad • June ‘97 NM95MS18 USER'S GUIDE Register Summary Following is a list of registers implemented on NM95MS18 Plug-n-Play controller. Registers located from 0x00 to 0x0F Word address are specific to NM95MS18 and are not part of registers defined

564-0700-444

Contextual Info: 3mm LED CBI Circuit Board Indicator Tri-Level Dialight 564-0x00-xxx PART NO. 4.32 [.170] MAX HIGH EFFICIENCY - LED TYPE 01 11.56 [.455] 2.62 [.103 ±.015] COLOR* 564-0100-111 564-0100-132 564-0100-222 564-0100-777 3.05 [.120] 5.08 [.200] Red-Red-Red Red-Yellow-Green

0x0002

Abstract: ADSP-21000 0X0040
Contextual Info: Interrupt Vector Addresses IRPTL/ IMASK Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Vector Address* 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54

Contextual Info: MM Registers - For a summary of all registers refer to the Register Summary section at the end of this chapter. All reserved bits must be written to a zero. NOTE: Control Registers 0x00— DS1/DS2 Output Control Register CR00

0X13

Abstract: 0x40 0b10000000 0B11000000
Contextual Info: The application code of PWM function. IOC9 = 0X9 IOCA = 0XA R10 = 0X10 ;PWM COUNTER R11 = 0X11 ;PWM COUNTER R12 = 0X12 ;TEMP R13 = 0X13 ;TEMP R14 = 0X14 ;TEMP ERE = 0XE ORG 0X000 INITIAL: MOV A,@0B11001000 ;SELECT EXTRA RAM IOW IOCA CLRA IOW IOC9 CLR R10

0B11000000

Abstract: 0X13 0b10000000
Contextual Info: 義隆電子股份有限公司 ELAN MICROELECTRONICS CORP. The application code of PWM function. IOC6 = 0X6 IOC8S = 0X8 R8S = 0X08 ;PWM COUNTER R9S = 0X09 ;PWM COUNTER R12 = 0X12 ;TEMP R13 = 0X13 ;TEMP R14 = 0X14 ;TEMP ERE = 0XE ORG 0X000 INITIAL:

564-0300-132

Abstract: LED r 3mm 564-0200-111
Contextual Info: 3mm LED CBI Circuit Board Indicator Tri Level 564-0x00-xxx PART NO. 4.32 [.170] 11.43 [.450] COLOR LED DATA SHEET HIGH EFFICIENCY - 0100 TYPE 564-0100-111 564-0100-222 564-0100-132 3.05 [.120] 5.08 [.200] R/R/R G/G/G R/Y/G 3HD-XXXX 15.24 [.600] 5.08 [.200]

eeprom

Abstract: Send 0x40
Contextual Info: AN-0973 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Erasing and Programming the Sequencing Engine EEPROM by Enrico Del Mastro This application note describes how to block erase the sequencing engine EEPROM space 0xFA;0x00 to 0xFB;0xFF and write

Contextual Info: PRELIMINARY TECHNICAL DATA AD6623 DATA SHEET a Four Channel, 104 MSPS Digital Transmit Signal Processor TSP Preliminary Technical Data AD6623 AD6622 mode by selecting bit 7 of address 0x000 low. An external Digital-to-Analog Converter (DAC) is all that is

0x748

Abstract: 0x768 SCANSTA101 LFSR 0X0043 0x798
Contextual Info: SCANSTA101 Quick Reference Registers Address 0x00 0x01 0x02 0x03 0x04 0x05 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x11 0x13 0x15 0x17 0x19 Register Start Status Interrupt Control Interrupt Status Setup Clock Divider LFSR Exponent LFSR LSB Seed LFSR MSB Seed LFSR LSB Result

Bs 159

Contextual Info: ; The application code of PDA function. ;= ;R17 ;R18 TEMP ;R19 TEMP ;R1A ;R1B ;R1C ;R1D ;R1E INCLUDE "REGISTER.DT" ORG 0x00 JMP INITIAL ORG 0X01 INTERRUPT1: DISI MOV A_TEMP,A SWAP A_TEMP SWAPA RSR MOV RSR_TEMP,A SWAPA STATUS MOV STATUS_TEMP,A

Contextual Info: TL16PNP100A STANDALONE PLUG-AND-PLAY PnP CONTROLLER SLLS200B - MARCH 1995 - REVISED MARCH 1996 PnP Card Autoconfiguration Sequence Compliant Supports TVvo Logical Devices Decodes 10-Bit I/O Address Location With Programmable 1-, 2-, 4-, 8-, 16-Byte Block

multibus ARCHITECTURE

Abstract: mcbsp tms 6000
Contextual Info: TMS320VC5416 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS095B – MARCH 1999 – REVISED OCTOBER 1999 D D D D D D D D D D D D D Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU

mip 291

Abstract: mip 290
Contextual Info: SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025 – AUGUST 1998 D D D D D D D D D D D D D Single-Chip Parallel Multiple Instruction / Multiple Data MIMD Digital Signal Processor (DSP) More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP)

Contextual Info: bq2945 Gas Gauge IC with SMBus Interface Features General Description ➤ Provides accurate measurement of available charge in NiCd, NiMH, and Li-Ion batteries The bq2945 Gas Gauge IC With SMBus Interface is intended for battery-pack or in-system installation to maintain an accurate record

TXC07900AIBG

Abstract: TXC-07900AIBG TSOP transmitter B020H OED155TM TXC-07900-MB VTXP-6 AU-AIS dk12b EK117
Contextual Info: OED155 Device Dual STM-1 Overhead Terminator, Tributary Processor and Cross-Connect with Integrated E1 Mapper TXC-07900 PRODUCT PREVIEW DATA SHEET DESCRIPTION: ™ The Optimized Edge Device, OED155, is a dual STM-1 SDH framer and overhead terminator, virtual tributary

Contextual Info: TLV5618A 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN SLAS230 – JULY 1999 features D D D D D D applications Dual 12-Bit Voltage Output DAC Programmable Internal Reference Programmable Settling Time

w12 diode

Abstract: PCI4450 PC MOTHERBOARD schematic diagram
Contextual Info: PCI4450 GFN/GJG PC Card and OHCI Controller SCPS046 – JANUARY 1999 D 1997 PC Standard Compliant D PCI Bus Power Management Interface D D D D D D D D D D D D D D D D D D D D Specification 1.1 Compliant ACPI 1.0 Compliant PCI Local Bus Specification Revision

VTXP-6

Abstract: TXC-06951 g803 Motorola 0X69 TXC-06951-MB 98822
Contextual Info: VTXP-6 Device STM-1/STS-3 SDH/SONET TU/VT Processor and Cross Connect TXC-06951 DATA SHEET PRELIMINARY TXC-06951-MB, Ed. 5 March 2006 FEATURES APPLICATIONS • Supports two line ports using the standard byte wide 19.44 MHz Telecom Bus, or a single line port using the standard byte wide 77.76 MHz Telecom Bus.

SLUS465b

Contextual Info: bq2019 ADVANCED BATTERY MONITOR IC SLUS465B – DECEMBER 1999 – REVISED DECEMBER 2000 D D D D D D D D D D D D Multifunction Monitoring IC Designed to Work With an Intelligent Host Controller – Provides State-of-Charge Information for Rechargeable Batteries

Contextual Info: 8 Bit Microcontroller TLCS-870/C1 Series TMP89FH46 The information contained herein is subject to change without notice. 021023_D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and

TC58NVG1S3ETA00

Abstract: TC58NVG1S3ET TC58NVG1S3 TC58NVG1S3ETA DIN2111
Contextual Info: TC58NVG1S3ETA00 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 2 GBIT 256M x 8 BIT CMOS NAND E PROM DESCRIPTION The TC58NVG1S3E is a single 3.3V 2 Gbit (2,214,592,512 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 2048blocks.