LH531000B Search Results

sharp lh53

Abstract: sharp lh53 1M
Contextual Info: CMOS 1M 128K x 8 Mask-Programmable ROM DESCRIPTION FEATURES • 131,072 x 8 bit organization • Access time: 150 ns (M AX.) • Low power consumption: The LH531000B is a mask-programmable ROM organized as 131,072 x 8 bits. It is fabricated using silicon-gate CMOS process technology.

lh531

Abstract: LH531000B LH531000BN-S LH531000B-S
Contextual Info: L H ^ I n n O R l v / V * v u v - C ^ CMOS 1M 128K x 8 w _ 3 V-D rive M a sk-P ro g ram m a ble ROM FEATURES DESCRIPTION • 131,072 words x 8 bit organization The LH531000B-S is a mask-programmable ROM organized as 131,072 x 8 bits. It is fabricated using

LH531000B

Abstract: LH531000BN-S LH531000B-S
Contextual Info: LH531000B-S CMOS 1M 128K x 8 3 V-Drive MROM FEATURES DESCRIPTION • 131,072 words × 8 bit organization The LH531000B-S is a mask-programmable ROM organized as 131,072 × 8 bits. It is fabricated using silicon-gate CMOS process technology. • Access time: 500 ns (MAX.)

sharp mask rom

Abstract: DIP028-P-0600
Contextual Info: CMOS 1M 128K x 8 Mask-Programmable ROM FEATURES DESCRIPTION • 131,072 words x 8 bit organization • Access time: 150 ns (MAX.) The LH531000B is a m ask-program mable ROM organized as 131,072 x 8 bits. It is fabricated using silicon-gate CMOS process technology.

mrom

Abstract: LH531000B
Contextual Info: LH531000B CMOS 1M 128K x 8 MROM FEATURES DESCRIPTION • 131,072 words × 8 bit organization The LH531000B is a mask-programmable ROM organized as 131,072 × 8 bits. It is fabricated using silicon-gate CMOS process technology. • Access time: 150 ns (MAX.)

431 capacitor NCC

Contextual Info: LH531000B CMOS 1M 128K x 8 Mask-Programmable ROM FEATURES DESCRIPTION • 1 31,072 x 8 bit organization The LH531000B is a mask-programmable ROM organized as 131,072 x 8 bits. It is fabricated using silicon-gate CMOS process technology. • Access time: 150 ns (M AX.)

LH531000B

Contextual Info: LH531000B CMOS 1M 128K x 8 Mask-Programmable ROM FEATURES DESCRIPTION • 131,072 words × 8 bit organization The LH531000B is a mask-programmable ROM organized as 131,072 × 8 bits. It is fabricated using silicon-gate CMOS process technology. • Access time: 150 ns (MAX.)

sharp mask rom

Contextual Info: CMOS 1 M 128 K x 8 MROM FEATURES DESCRIPTION • 131,072 words x 8 bit organization The LH531000B is a m ask-program m able ROM organized as 131,072 x 8 bits. It is fabricated using silicon-gate CMOS process technology. • Access time: 150 ns (MAX.) • Low power consumption:

sharp mask rom 44-pin

Abstract: 1417D lh53
Contextual Info: CMOS 1M 128K x 8 Mask-Programmable ROM FEATURES DESCRIPTION • 131,072 x 8 bit organization The LH531000B is a mask-programmable ROM organized as 131,072 x 8 bits. It is fabricated using silicon-gate C M O S process technology. • Access time: 150 ns (MAX.)

Contextual Info: LH531000B-S CMOS 1M 128K x 8 3 V-Drive Mask-Programmable ROM FEATURES DESCRIPTION • 131,072 words x 8 bit organization The LH531000B-S is a mask-programmable ROM organized as 131,072 x 8 bits. It is fabricated using silicon-gate CMOS process technology.

sharp lh531

Abstract: sharp mask rom
Contextual Info: CMOS 1M 128K FEATURES • 131,072 x 8 bit organization • Access time: 150 ns (MAX. • Low power consumption: Operating: 192.5 mW (MAX.) x 8) Mask Programmable ROM DESCRIPTION The LH531000B is a mask programmable ROM organized as 131,072 x 8 bits. It is fabricated using

sharp mask rom 44-pin

Abstract: sharp mask rom LH53 DIP28-P-600 L3433
Contextual Info: S HARP CORP LH531000B L IE 131,072 x 8 bit organization • Access time: 150 ns MAX. • Low power consumption: Operating: 192.5 mW (MAX.) û lfl07T fl CMOS 1M (128K FEATURES • D x DGDT ÛS M Tb4 ISRPJ 8) Mask-Programmable ROM DESCRIPTION The LH531000B is a mask-programmable ROM

536G

Abstract: LH534600
Contextual Info: MEMORIES • Mask ROMs Process Capacity * Configuration words X bits Pinout Access time Model No. (ns) MIN. Supply current (mA) MAX. Supply voltage (V) (ns) MAX. User's No. Cycle tima Package 256k 32k X 8 J LH53259D/N/T L H 5359X X 150 25 5 ± 10% 28DIP/28SOP/28TSOP(I)

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

lh5s4

Abstract: lh537 48-TSOP LH5s 42-DIP 48TSOP1 LH5364P00D LH538 LH5S46
Contextual Info: MEMORIES • Mask ROM Specific Pinout ★ U n d e rd e v e lo p m e n t • 3 V 3 .3 V operation Access time B it C a p a c ity configuration 1M x8 2M x 8/x 16 4M x 8/x 16 8M x 8/x 16 16M x 8/x 16 32 M x 8/x 16 64M 128M * x 8/x 16 x 16 Readable at 2.7 V.

flash 64m

Contextual Info: MEMORIES Mask ROMs C a p a c ity Access time C o nfig u ra tio n 120ns 100ns 80ns 150ns 256kj I 32k x 8 ] LH53259 12k I 64k x 8 LH53517 128k x 8 LH530800A LH531V00 1M LH531024 64k x 16 i LH532100B-1 256k x 8 ! LH532100B 2M JEDEC standard EPROM pinout 128k x 161

LQ070T5BG01

Abstract: LM24P20 LM162KS1 BSCR86L00 IR2C07 LM5Q31 IR3Y29B BSCU86L60 lq6bw lq6bw506
Contextual Info: INDEX 1 0 4 - 1 0 9 _ DC_ GL1PR112.69 GL3KG63. 66 GL5EG41.66 1 0 4 - n 0 5 O o c .113 DC1B1CP. 100 GL1PR135.69 GL3KG8. 66

Contextual Info: MEMORIES ★ Capacity Configuration * 1 C om patible with 4 M -bit flash m em ories from A d vanced M icro D evices, Inc. * 2 C om patible with 4 M -bit flash m em ories from Intel Corp. A c c e s s tim e Under development MEMORIES ★ Under development Access time

IR3Y29B

Abstract: ir3y26a1 IR4N IR3T24N IR3C08N ir2c53 ir2c05 li3301 IR3Y08 IR2E02
Contextual Info: Index Model No. IR3T ARM710 ARM7DI ARM7DM ARM7TDMI ARM7TDMI-SPL ARM8 ARM810 CMOS CMOS CMOS CMOS F series G series J series K series ID22 series ID222XX ID223XX ID224XX ID226XX ID227XX ID229XX ID22DXX ID22FXX ID22HXX ID240 series ID240DXX ID240EXX ID240GXX

48 tsop flash pinout

Abstract: LH23512
Contextual Info: MEMORIES Mask ROMs ^Under development Capacity Pinout Model No. Configuration Access time ns 55 1 64k !- 1 8k x 8 128k 16k x ! 256k 32k x 8 |- -) [ 512k 64k x 8 b — I 80 100 120 150 200 Package 250 500 □ LH2369 28 LH23255 28 □ LH53259 28 28 38(1)

lh5359

Abstract: e5bx
Contextual Info: Ffe MASK ROM * ★ • MASK ROMs New product Under development * Features • Product lineup covers 11 capacity ranges from 256 k-bit to 128 M-bit. • Product variations with 3 types o f pinout including JEDEC standard EPROM, Mask ROM specific and Flash memory compatible pinout.

IR2E27A

Abstract: IR2C53 IR2E02 IR2E27 IR2E10 IR3N34 IR2E31A IR2E01 IR2C07 ir2e31
Contextual Info: lndeX Model No. ARM7D CPU Core28,32,33 ARM7DM 28,33 CMOS CMOS CMOS CMOS 76 5A A F G 44 44 44 44 ID1 series ID2 series ID3 seríes ID21K064 ID21K128 ID21K256 ID21K512 ID21M010 ID21M015 ID21M020 ID21M040 ID22K256 ID22K512 ID22M010 ID22M020 ID22M040 ID22M080