HCT107 Search Results

Contextual Info: 74HC/HCT107 flip-flops D U A L JK FLIP-F LO P W ITH R E SE T ; N E G A T IV E -E D G E T R IG G E R FEATURES T Y P IC A L • Output capability: standard • I q q category: flip-flops SYM BO L T h e reset {n R is an asy n ch ron ou s active L O W input. W hen L O W , it overrides the

Contextual Info: High-Reliability High-Speed CMOS Logic ICs CD54HC107/3A HCT107/3A Burn-ln Test-Circuit Connections Static OPEN CD54HC/HCT107 2,3,5,6 Dynamic GROUND OPEN CD54HC/HCT107 Use Static II for /3A burn-in and Dynamic for Life Test. STATIC BURN-IN I Vcc(6V) GROUND

220 NK

Abstract: 74HC 74HCT 7Z9319
Contextual Info: 74HC/HCT107 flip-flops DUAL JK FLIP-FLOP WITH RESET; NEGATIVE-EDGE TRIGGER FEATURES • • TYPICAL Output capability: standard ICC category: flip-flops GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky

Contextual Info: 74HC/HCT107 fiip-fiops DUAL JK FLIP-FLOP WITH RESET; NEGATIVE-EDGE TRIGGER FEA TU R E S • • TYPICAL O utput capability: standard I q c category: flip-flops SYMBOL The 74HC/HCT107 are dual negativeedge triggered JK-type flip-flops _ featuring individual J, K, clock nCP

74HC

Abstract: TTL Schmitt-Trigger LOW POWER SCHOTTKY
Contextual Info: Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107 The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock nCP and reset (nR) inputs; also complementary Q and Q outputs.

74HC/HCT/HCU/HCMOS Logic Family Specifications

Abstract: 74HC/HCT/HCU/HCMOS Logic Package Information IC06 74HC/HCT/HCU/HCMOS Logic Package Information 74HC 74HCT HCT107
Contextual Info: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT107

Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description

CD74HCT107

Abstract: CD54HC107F3A CD54HCT107F3A CD74HC107E HC107 HCT10
Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/HCT107 Data sheet acquired from Harris Semiconductor SCHS139B Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised December 2002

HC-107

Abstract: HC107
Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/HCT107 Data sheet acquired from Harris Semiconductor SCHS139A Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised May 2000 Features

CD54HC73

Abstract: CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M CD74HCT73 HC73
Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description

CD54HC73

Abstract: CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M CD74HCT73 HC73
Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description

Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description

BPW22A

Abstract: cm .02m z5u 1kv pin configuration of BFW10 la4347 B2X84 TDA3653 equivalent TRIAC TAG 9322 HEF40106BP equivalent fx4054 core dsq8
Contextual Info: Contents Page Page New product index Combined index and status codes viii x Mullard approved components BS9000, CECC, and D3007 lists CV list Integrated circuits Section index xliii 1 5 Standard functions LOGIC FAMILIES CMOS HE4000B family specifications CMOS HE4000B family survey

Contextual Info: INTEGRATED CIRCUITS [M m S P I E 74LV107 Dual JK flip-flop with reset; negative-edge trigger Product specification Supersedes data of 1997 Feb 03 IC24 Data Handbook Philips Semiconductors 1998 Apr 20 PHILIPS Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger

Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54/74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134C Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised January 2003 Features Description • Hysteresis on Clock Inputs for Improved Noise

CD54HC73

Abstract: CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M CD74HCT73 HC73
Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description

Contextual Info: CD74HC73, CD74HCT73 ^ Texas In s t r u m e n t s Data sheet acquired from Harris Semiconductor SCHS134 Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times

Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description

74LV107

Abstract: 74LV107D 74LV107DB 74LV107N
Contextual Info: Philips Semiconductors Product Specification Dual JK flip-flop with reset; negative-edge trigger FEATURES • • • • • • 74LV107 QUICK REFERENCE DATA GNP = 0 V; T*, = 25 °C; t, = t, < 2.5 ns Optimized fo r Low Voltage applications: 1.0 to 3.6 V

Contextual Info: CD74HC73, CD74HCT73 S E M I C O N D U C T O R Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times The Harris CD74HC73 and CD74HCT73 utilize silicon gate

74HCT

Abstract: 74LS CD74HC73 CD74HC73E CD74HCT73 CD74HCT73E HC73
Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134 Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise

HS-134

Contextual Info: CD74HC73, CD74HCT73 ^ Texas In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SC HS134 Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times

Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description

74HC73

Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54/74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134A Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised May 2000 Features Description • Hysteresis on Clock Inputs for Improved Noise