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    HCT10 Search Results

    HCT10 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CD74HCT10M
    Texas Instruments High Speed CMOS Logic Triple 3-Input NAND Gates 14-SOIC -55 to 125 Visit Texas Instruments Buy
    CD74HCT10M96G4
    Texas Instruments High Speed CMOS Logic Triple 3-Input NAND Gates 14-SOIC -55 to 125 Visit Texas Instruments Buy
    CD74HCT109M
    Texas Instruments High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 Visit Texas Instruments Buy
    CD74HCT10M96
    Texas Instruments High Speed CMOS Logic Triple 3-Input NAND Gates 14-SOIC -55 to 125 Visit Texas Instruments Buy
    CD74HCT109E
    Texas Instruments High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 Visit Texas Instruments Buy

    HCT10 Datasheets (2)

    Select Manufacturer
    Part ECAD Model Manufacturer Description Datasheet Type PDF PDF Size Page count
    HCT10
    System Logic Semiconductor Triple 3-Input NAND Gate(High-Performance Silicon-Gate CMOS) Original PDF 33.64KB 4
    HCT-100
    InfraRed Associates Mercury Cadmium Telluride - HgCdTe Detectors Scan PDF 187.78KB 1
    SF Impression Pixel

    HCT10 Price and Stock

    Nexperia

    Nexperia 74HCT109PW,118

    Flip Flop, 74HCT109, JK, 17 ns, 61 MHz, 4 mA, 16 Pins, TSSOP - Tape and Reel (Alt: 74HCT109PW,118)
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Avnet Americas 74HCT109PW,118 Tape & Reel 16 Weeks 5,000
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    Mouser Electronics 74HCT109PW,118 1,883
    • 1 $0.46
    • 10 $0.32
    • 100 $0.25
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    Rochester Electronics 74HCT109PW,118 47,040 1
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    Avnet Silica 74HCT109PW,118 26 Weeks 2,500
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    Vyrian 74HCT109PW,118 2,549
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    Nexperia 74HCT10D,653

    NAND Gate, Triple, 3 Input, 14 Pins, SOIC, 74HCT10 - Tape and Reel (Alt: 74HCT10D,653)
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    Avnet Americas 74HCT10D,653 Tape & Reel 24 Weeks 7,500
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    Mouser Electronics 74HCT10D,653
    • 1 $0.28
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    Rochester Electronics 74HCT10D,653 91 1
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    TME 74HCT10D,653 1
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    Avnet Asia 74HCT10D,653 24 Weeks 7,500
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    Avnet Silica 74HCT10D,653 26 Weeks 2,500
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    Nexperia 74HCT107D-Q100J

    Flip Flop JK-Type Neg-Edge 2-Element 14-Pin SOIC T/R - Tape and Reel (Alt: 74HCT107D-Q100J)
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Avnet Americas 74HCT107D-Q100J Tape & Reel 16 Weeks 5,000
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    Mouser Electronics 74HCT107D-Q100J
    • 1 $0.56
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    Rochester Electronics 74HCT107D-Q100J 36,866 1
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    Nexperia 74HCT10PW-Q100J

    NAND Gate, Triple, 3 Input, 14 Pins, TSSOP, 74HCT10 - Tape and Reel (Alt: 74HCT10PW-Q100J)
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Avnet Americas 74HCT10PW-Q100J Tape & Reel 24 Weeks 5,000
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    Mouser Electronics 74HCT10PW-Q100J
    • 1 $0.46
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    Avnet Silica 74HCT10PW-Q100J 26 Weeks 2,500
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    Nexperia 74HCT10D-Q100J

    NAND Gate, Triple, 3 Input, 14 Pins, SOIC, 74HCT10 - Tape and Reel (Alt: 74HCT10D-Q100J)
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Avnet Americas 74HCT10D-Q100J Tape & Reel 24 Weeks 7,500
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    Avnet Silica 74HCT10D-Q100J 26 Weeks 2,500
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    HCT10 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    HC10

    Abstract: CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HCT10
    Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, HCT10, HCT10


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    hct10cd54hc10cd74hc10cd54hct10+6cd74hct10schs128chc10cd54hc10f3acd54hct10f3acd74hc10e PDF

    CD74HCT107

    Abstract: CD54HC107F3A CD54HCT107F3A CD74HC107E HC107 HCT10
    Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/HCT107 Data sheet acquired from Harris Semiconductor SCHS139B Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised December 2002


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    hc107hct10cd54/74hc107cd54/74hct107+6schs139bhct107cd74hct107cd54hc107f3acd54hct107f3acd74hc107e PDF

    HC-107

    Abstract: HC107
    Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/HCT107 Data sheet acquired from Harris Semiconductor SCHS139A Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised May 2000 Features


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    hc107hct10cd54/74hc107cd54/74hct107+3schs139ahct107hc-107 PDF

    KK74AC109

    Abstract: KK74AC109D KK74AC109N
    Contextual Info: TECHNICAL DATA KK74AC109 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The KK74AC109 is identical in pinout to the LS/ALS109,HC/HCT109. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LS/ALS outputs.


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    kk74ac109ls/als109hc/hct109012ac+2kk74ac109dkk74ac109n PDF

    HC107

    Abstract: 74HCT 74LS CD74HC107 CD74HC107E CD74HCT107 CD74HCT107E HCT10
    Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD74HC107, HCT107 Data sheet acquired from Harris Semiconductor SCHS139 Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times


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    hc107hct10cd74hc107cd74hct107+5schs13974hct74lscd74hc107ecd74hct107e PDF

    Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, HCT10, HCT10


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    cd54hc10cd74hc10cd54hct10cd74hct10+2schs128chct10 PDF

    HCT10

    Abstract: CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10
    Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, HCT10, HCT10


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    hct10cd54hc10cd74hc10cd54hct10+6cd74hct10schs128ccd54hc10f3acd54hct10f3acd74hc10ehc10 PDF

    Contextual Info: 74HC/HCT107 flip-flops D U A L JK FLIP-F LO P W ITH R E SE T ; N E G A T IV E -E D G E T R IG G E R FEATURES T Y P IC A L • Output capability: standard • I q q category: flip-flops SYM BO L T h e reset {n R is an asy n ch ron ou s active L O W input. W hen L O W , it overrides the


    OCR Scan
    74hc/hct107 PDF

    CD54HC107

    Abstract: CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HC107 HCT10
    Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003


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    hc107hct10cd54hc107cd74hc107+5cd74hct107schs139dcd54hc107f3acd74hc107ecd74hc107m PDF

    CD54HC10

    Abstract: CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 HCT10
    Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, HCT10, HCT10


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    hct10cd54hc10cd74hc10cd54hct10+6cd74hct10schs128ccd54hc10f3acd54hct10f3acd74hc10ehc10 PDF

    Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003


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    cd54hc107cd74hc107cd74hct107schs139d+2hc107hc/hct73 PDF

    IN74ACT109D

    Abstract: IN74ACT109N
    Contextual Info: IN74ACT109 DUAL J-K FLIP-FLOP WITH SET AND RESET High-Speed Silicon-Gate CMOS • • • • The IN74ACT109 is identical in pinout to the LS/ALS109, HC/HCT109. The IN74ACT109 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.


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    in74act109ls/als109hc/hct109in74act109d+1in74act109n PDF

    HC-86

    Abstract: HC09 hcoo HC07 hc86 hc132 HC123A HC-107 HC251 HC4050
    Contextual Info: SELECTION GUIDE FUNCTION GATE BUFFER FLIP-FLOP STANDARD CODE NAND HCOO, HCTOO, HC03, HC10, HCT10, HC20, HC30, HC133, HCT30 NOR HC02, HCT02, HC27, HCT27, HC4002, HC4078 AND HC08, HCT08, HC09, HC11, HC21 OR HC32, HCT32, HC4072, HC4075 EX NOR HC266, HC7266 EX OR


    OCR Scan
    hct10hc133hct30hct02+16hct27hc4002hc4078hct08hct32hc4072hc-86hc09hcoohc07hc86hc132hc123ahc-107hc251hc4050 PDF

    IN74AC109

    Abstract: IN74AC109D IN74AC109N
    Contextual Info: TECHNICAL DATA IN74AC109 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74AC109 is identical in pinout to the LS/ALS109,HC/HCT109. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible


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    in74ac109ls/als109hc/hct109in74ac109d+1in74ac109n PDF

    IN74AC10N

    Abstract: IN74AC10D
    Contextual Info: TECHNICAL DATA IN74AC10 Triple 3-Input NAND Gate High-Speed Silicon-Gate CMOS The IN74AC10 is identical in pinout to the LS/ALS10, HC/HCT10. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS


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    in74ac10ls/als10hc/hct10in74ac10n+1in74ac10d PDF

    Contextual Info: Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LVC109 FEATURES DESCRIPTION • Wide supply voltage range of 1.2 to 3.6 V The 74LVC1G9 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109.


    OCR Scan
    74lvc10974lvc1g974hc/hct109sv00904 PDF

    "J-K Flip flop"

    Abstract: CD54HC107F3A HC107 T flip flop IC CD54HC107 CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HCT10
    Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003


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    hc107hct10cd54hc107cd74hc107+7cd74hct107schs139dj-k flip flopcd54hc107f3at flip flop iccd74hc107ecd74hc107m PDF

    74HC/HCT/HCU/HCMOS Logic Family Specifications

    Abstract: 74HC/HCT/HCU/HCMOS Logic Package Information 74HC/HCT/HCU/HCMOS Logic Package Outlines IC06 74HC/HCT/HCU/HCMOS Logic Package Information Package Information philips IC06 74HC Logic Family Specifications logic family specification philips ic06 HCT10 IC06 74HC/HCT/HCU/HCMOS Logic Package Outline The IC06 74HC/HCT/HCU/HCMOS Logic Package
    Contextual Info: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT10


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    74hc/hct/hcu/hcmos74hc/hct1074hct74hc/hct/hcu/hcmos logic family specifications+974hc/hct/hcu/hcmos logic package information74hc/hct/hcu/hcmos logic package outlinesic06 74hc/hct/hcu/hcmos logic package informationpackage information philips ic0674hc logic family specificationslogic family specification philips ic06hct10ic06 74hc/hct/hcu/hcmos logic package outlinethe ic06 74hc/hct/hcu/hcmos logic package PDF

    HC107

    Abstract: CD54HC107 CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HCT10
    Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, HCT107 Data sheet acquired from Harris Semiconductor SCHS139C Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised May 2003


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    hc107hct10cd54hc107cd74hc107+5cd74hct107schs139ccd54hc107f3acd74hc107ecd74hc107m PDF

    CD54HC10

    Abstract: CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 HCT10
    Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, HCT10, HCT10


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    hct10cd54hc10cd74hc10cd54hct10+6cd74hct10schs128bcd54hc10f3acd54hct10f3acd74hc10ehc10 PDF

    Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003


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    cd54hc107cd74hc107cd74hct107schs139d+2hc107hc/hct73 PDF

    74hct10

    Abstract: 74HC10
    Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54/74HC10, CD54/HCT10 Data sheet acquired from Harris Semiconductor


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    cd54/74hc10cd54/74hct10schs128ahct10+7sdya012sn54/74hctscla011scla008szzu001b74hct1074hc10 PDF

    KK74ACT10

    Abstract: KK74ACT10D KK74ACT10N
    Contextual Info: TECHNICAL DATA KK74ACT10 Triple 3-Input NAND Gate High-Speed Silicon-Gate CMOS The KK74ACT10 is identical in pinout to the LS/ALS10, HC/HCT10. The KK74ACT10 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. • TTL/NMOS Compatible Input Levels


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    kk74act10ls/als10hc/hct10kk74act10n+2kk74act10d012ab PDF

    CD74HC10E

    Abstract: CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HCT10 HC10 HCT10
    Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, HCT10, HCT10


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    hct10cd54hc10cd74hc10cd54hct10+6cd74hct10schs128ccd74hc10ecd54hc10f3acd54hct10f3ahc10 PDF