74HCT10 Search Results

74HC109

Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140A Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised May 2000 Features

CD74HCT107

Abstract: CD54HC107F3A CD54HCT107F3A CD74HC107E HC107 HCT10
Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/74HCT107 Data sheet acquired from Harris Semiconductor SCHS139B Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised December 2002

HC-107

Abstract: HC107
Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/74HCT107 Data sheet acquired from Harris Semiconductor SCHS139A Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised May 2000 Features

Contextual Info: 74HC107; 74HCT107 Dual JK flip-flop with reset; negative-edge trigger Rev. 3 — 18 November 2013 Product data sheet 1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock CP and reset (R) inputs and complementary Q and Q

74HC107

Contextual Info: Technical Data CD54/74HC107 CD54/74HCT107 File N u m b e r 1722 High-Speed CMOS Logic Dual J-K Flip-Flop with Reset N egative-E d g e T rigger Type Features: • zr GND * 7 v c c *14 92CS- 594 16 H y s te re s is o n c lo c k in p u ts fo r im p ro v e d n o is e im m u n ity a n d in c re a s e d

74hc10

Abstract: 74HCT10
Contextual Info: Technical Data_ CD54/74HC10 CD54/74HCT10 F ile N u m b e r 1551 High-Speed CMOS Logic Triple 3-Input NAND Gate Type Features: • B u ffe re d inpu ts • Typical propagation delay = 8 ns @ V'cc = 5 V, C L = 15 pF, I A = 25° C FUNCTIONAL DIAGRAM AND TERMINAL ASSIGNMENT

Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140B Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised December 2002

Contextual Info: Technical Data_ _ CD54/74HC10 CD54/74HCT10 F ile N u m b e r 1551 High-Speed CMOS Logic Triple 3-Input NAND Gate Type Features: • B u ffe re d inputs ■ Typical propagation delay = 8 ns @ V c c = 5 V, CL = 75 pF, 7"a = 25° C

74hct10

Abstract: 74HC10
Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54/74HC10, CD54/74HCT10 Data sheet acquired from Harris Semiconductor

HCT109 harris

Abstract: 74HCT109
Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140A Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised May 2000 Features

74HC107PW

Contextual Info: 74HC107-Q100; 74HCT107-Q100 Dual JK flip-flop with reset; negative-edge trigger Rev. 1 — 18 November 2013 Product data sheet 1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock CP and reset (R) inputs and complementary Q

74hct10

Abstract: 74HC10 PF7A L68G
Contextual Info: G Technical Data. E SOLI» STATE 01 j>r| 3fl7SDfll 0G114SS 4 - T ^ 3 - - Z I CD54/74HC10 CD54/74HCT10 File Number 1551 High-Speed CMOS Logic Triple 3-Input NAND Gate Type Feature«: • Buffered inputs a Typical propagation delay = 8ns

CD74HC109E

Abstract: HC109 C109 CD54HC109F3A CD54HCT109F3A
Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140B Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised December 2002

Contextual Info: - Technical Data File N um b er 1667 CD54/74HC109 C D54/74HCT109 High-Speed CMOS Logic Duai J-K Flip-Flop with Set and Reset Type Features: 9 2 C S -36532 • Positive-Edge triggered • A s y n c h ro n o u s S et a n d Reset m 60 M Hz Typical M axim um C lo ck Frequency

74HCT10

Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54/74HC10, CD54/74HCT10 Data sheet acquired from Harris Semiconductor

GD74HCT10

Abstract: GD74HC10
Contextual Info: GD54/74HC10, GD54/74HCT10 TRIPLE 3-INPUT NAND GATES General Description These devices are identical in pinout to the 5 4 /74 L S 1 0. They contain three independent 3-input NAND gates. These devices are characteriz­ ed for operation over wide temperature ranges to

Contextual Info: GD54/74HC107, GD54/74HCT107 DUAL J-K FLIP-FLOPS WITH CLEAR General Description These devices are identical in pinout to the 5 4 /7 4 L S 1 0 7 . They consist of two J-K flip-flops with individual J, K, clock, and clear inputs. These flipflops are edge sensitive to the clock input and

74HC10

Abstract: 74HCT10
Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54/74HC10, CD54/74HCT10 Data sheet acquired from Harris Semiconductor

Contextual Info: Technical Data CD54/74HC107 CD54/74HCT107 File N um ber 1722 High-Speed CMOS Logic Dual J-K Flip-Flop with Reset N egative-E dge T rigg er Type Features: • _ x GNO • 7 Vcc ' 14 92CS - 39416 H ysteresis on c lo c k in p u ts fo r im proved noise im m u n ity a n d increased

Contextual Info: GD54/74HC109, GD54/74HCT109 DUAL J-K FLIP-FLOPS W ITH PRESET & CLEAR General Description are identical in pinout with individual J, K, Clock, Preset, to Pin Configuration the flip-flops and Clear U IC L R p T inputs. T h e s e flip-flops are e d g e sensitive to the

74HC107

Contextual Info: t-Hu-ch- r j Technical D ata _ — CD54/74HC107 CD54/74HCT107 r ile N u m b e r 1722 High-Speed CMOS Logic HARR IS S E M I C O N D S E CT OR 27E D 4 3 0 5 27 1 0 Q 1 7 S 4 1 E 3 •HAS Dual J-K Flip-Flop with Reset N egative-E d g e T rigg er

74HCT10

Contextual Info: 1 ' 4 3 -Z/-CO Technical Data_ CD54/74HC10 CD54/74HCT10 HARRIS SEMICOND File Number 1551 SECTOR 27E D 430H271 0017475 5 *HAS High-Speed CMOS Logic Triple 3-Input NAND Gate Type Features: • B u tte re d inpu ts • Typical propagation delay = 8 ns @ Vcc = 5 V, CL = 15 pF, TA = 25° C

HC-107

Abstract: hc107
Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/74HCT107 Data sheet acquired from Harris Semiconductor SCHS139B Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised December 2002

125oCMIN

Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/74HCT107 Data sheet acquired from Harris Semiconductor SCHS139B Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised December 2002