CD74HCT73 Search Results
CD74HCT73 Result Highlights (3)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
|---|---|---|---|---|---|
| CD74HCT73M96 | Texas Instruments | High speed CMOS logic dual negative-edge-triggered J-K flip-flops with reset 14-SOIC -40 to 125 |
|
||
| CD74HCT73M | Texas Instruments | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 |
|
|
|
| CD74HCT73E | Texas Instruments | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 |
|
|
CD74HCT73 Datasheets (23)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CD74HCT73 | Texas Instruments | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Original | 56.28KB | 8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73 | Texas Instruments | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset | Original | 45.5KB | 8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73E | Texas Instruments | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Original | 149.6KB | 11 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73E | Texas Instruments | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 | Original | 455.21KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73E | Texas Instruments | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Original | 56.28KB | 8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73E | Texas Instruments | CD74HCT73 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 | Original | 633.59KB | 17 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73E | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 38.78KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73E96 | Texas Instruments | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Original | 45.51KB | 8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73EE4 | Texas Instruments | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Original | 280.47KB | 13 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73EE4 | Texas Instruments | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 | Original | 455.21KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73EE4 | Texas Instruments | CD74HCT73 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 | Original | 633.59KB | 17 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73EG4 | Texas Instruments | Integrated Circuits (ICs) - Logic - Flip Flops - IC FF JK TYPE DUAL 1BIT 14DIP | Original | 632.89KB | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73M | Texas Instruments | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET | Original | 56.27KB | 8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73M | Texas Instruments | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Original | 149.6KB | 11 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73M | Texas Instruments | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 | Original | 455.21KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73M | Texas Instruments | CD74HCT73 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 | Original | 633.59KB | 17 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73M | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 38.78KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73M96 | Texas Instruments | CD74HCT73 - IC HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, MS-012, SOIC-14, FF/Latch | Original | 633.59KB | 17 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73ME4 | Texas Instruments | Dual J-K Flip-Flop with Reset Negative-Edge Trigger | Original | 280.47KB | 13 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HCT73ME4 | Texas Instruments | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 | Original | 455.21KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CD74HCT73 Price and Stock
Harris Semiconductor CD74HCT73EFlip Flop JK-Type Neg-Edge Push-Pull 2-Element 14-Pin PDIP Tube |
|||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|
CD74HCT73E | 12 |
|
Get Quote | |||||||
|
CD74HCT73E | 3 |
|
Buy Now | |||||||
|
CD74HCT73E | 675 |
|
Buy Now | |||||||
Texas Instruments CD74HCT73N |
|||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|
CD74HCT73N | 336 |
|
Buy Now | |||||||
Harris Semiconductor CD74HCT73D |
|||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|
CD74HCT73D | 164 |
|
Buy Now | |||||||
Texas Instruments CD74HCT73MJ-K FLIP-FLOP, HCT SERIES, 2-FUNC, NEGATIVE EDGE TRIGGERED, 2-BIT, COMPLEMENTARY OUTPUT, CMOS, PDSO14 |
|||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|
CD74HCT73M | 156 |
|
Buy Now | |||||||
Texas Instruments CD74HCT73EIC: digital; JK flip-flop; Ch: 2; CMOS; THT; DIP14; HCT; tube |
|||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|
CD74HCT73E | 888 | 1 |
|
Buy Now | ||||||
CD74HCT73 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
|
Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
cd54hc73cd74hc73cd74hct73schs134e+1 | |
CD54HC73
Abstract: CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M CD74HCT73 HC73
|
Original |
hct73cd54hc73cd74hc73cd74hct73+5 | |
CD54HC73
Abstract: CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M CD74HCT73 HC73
|
Original |
hct73cd54hc73cd74hc73cd74hct73+5 | |
|
Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
cd54hc73cd74hc73cd74hct73schs134e+1 | |
|
Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54/74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134C Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised January 2003 Features Description • Hysteresis on Clock Inputs for Improved Noise |
Original |
cd54/74hc73cd74hct73schs134chc/hct107+5 | |
|
Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54/74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134C Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised January 2003 Features Description • Hysteresis on Clock Inputs for Improved Noise |
Original |
cd54/74hc73cd74hct73schs134chc/hct107 | |
CD54HC73
Abstract: CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M CD74HCT73 HC73
|
Original |
hct73cd54hc73cd74hc73cd74hct73+5 | |
|
Contextual Info: CD74HC73, CD74HCT73 ^ Texas In s t r u m e n t s Data sheet acquired from Harris Semiconductor SCHS134 Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times |
OCR Scan |
cd74hc73cd74hct73schs134 | |
|
Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
cd54hc73cd74hc73cd74hct73schs134e+1 | |
|
Contextual Info: CD74HC73, CD74HCT73 S E M I C O N D U C T O R Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times The Harris CD74HC73 and CD74HCT73 utilize silicon gate |
Original |
cd74hc73cd74hct73hc/hct10774hct+1 | |
74HCT
Abstract: 74LS CD74HC73 CD74HC73E CD74HCT73 CD74HCT73E HC73
|
Original |
hct73cd74hc73cd74hct73schs134+5 | |
HS-134Contextual Info: CD74HC73, CD74HCT73 ^ Texas In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SC HS134 Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times |
OCR Scan |
hs134cd74hc73cd74hct73hc/hct107+1 | |
|
Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
cd54hc73cd74hc73cd74hct73schs134e+1 | |
74HC73Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54/74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134A Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised May 2000 Features Description • Hysteresis on Clock Inputs for Improved Noise |
Original |
cd54/74hc73cd74hct73schs134ahc/hct107+6 | |
|
|
|||
CD54HC73
Abstract: CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M CD74HCT73 HC73
|
Original |
hct73cd54hc73cd74hc73cd74hct73+5 | |
|
Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
cd54hc73cd74hc73cd74hct73schs134e+1 | |
cd54hc73f
Abstract: CD54HC73 CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M CD74HCT73 HC73
|
Original |
hct73cd54hc73cd74hc73cd74hct73+6 | |
cd54hc73f
Abstract: CD54HC73 CD54HC73F3A CD74HC73 CD74HC73E CD74HC73M CD74HCT73 HC73
|
Original |
hct73cd54hc73cd74hc73cd74hct73+6 | |
|
Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
cd54hc73cd74hc73cd74hct73schs134e+1 | |
|
Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
cd54hc73cd74hc73cd74hct73schs134e+1 | |
|
Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
cd54hc73cd74hc73cd74hct73schs134e+1 | |
|
Contextual Info: ASSESS? CD74HC73, CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times The Harris CD74HC73 and CD74HCT73 utilize silicon gate |
OCR Scan |
cd74hc73cd74hct73hc/hct10774hct | |
|
Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
hct73cd54hc73cd74hc73cd74hct73+1 | |
|
Contextual Info: [ /Title CD74 HC73, CD74 HCT73 /Subject (Dual J-K FlipFlop CD54HC73, CD74HC73, CD74HCT73 Data sheet acquired from Harris Semiconductor SCHS134E Dual J-K Flip-Flop with Reset Negative-Edge Trigger February 1998 - Revised September 2003 Features Description |
Original |
cd54hc73cd74hc73cd74hct73schs134e+1 | |