DQ09 Search Results

iei9

Contextual Info: I 31 I File No.I 3 5 3 eri 04.3 ID I'D 1 lnsulator:ABS, UL94HB RoH S Compliant 4.9 CM 1 / SPECIFICATIONS 8.00 20.2 09.8 I I SHEET l< in 6.9 16.5 2.6 20.5 CN 7.9 30.5 15.8 10.4 in ro Color Gray Black Chrome Plated Beige DQ09C DQ09B P/N: DQ09G DQ09K CATEGORY

AS8S512K3

Contextual Info: ADVANCED iPEM 64 Mb ASYNC SRAM AS8S2M32PEC 64Mb, 2Mx32 CMOS 3.3V, High Speed Static RAM Integrated Plastic Encapsulated Microcircuit FEATURES DESCRIPTION Integrated Real-Time Memory Array Solution No latency or refresh cycles Parallel Read/Write Interface

Memory

Abstract: FTS8L32512V
Contextual Info: FTS8L32512V 512Kx32 SRAM Module.3.3V FEATURES DESCRIPTION DSP Memory Solution The FTS8L32512V is a high speed, 3.3V, 16 megabit SRAM. The device is available with access times of 12, 15, 17 and 20ns allowing the creation of a no wait state DSP and RISC microprocessor memory solutions.

Contextual Info: Mobile 3rd Generation Intel Core Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron® Processor Family Datasheet, Volume 1 of 2 June 2013 Document Number: 326768-006 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,

Contextual Info: EDI8F32123C ^ E D I ELECTRONIC DESIGNS, N C .I 128Kx32 Battery Backed SRAM Module ADVANCED Features 128Kx32 bit CMOS Static Random Access Memory with on-board battery backup 128Kx32 Static RAM CMOS, High Speed Module The EDI8F32123C is a 4 megabit Battery Backed SRAM

socket am3 pinout

Abstract: socket AM2 pinout AM3 Processor Functional INTEL 80960 pipeline architecture 80960RM
Contextual Info: Intel 80960RM I/O Processor • ■ Complies with PCI Local Bus Specification, Revision 2.2 Universal 5 V and 3.3 V PCI Signalling Environment (C-stepping only) Data Sheet Product Features ■ ■ ■ ■ High Performance Intel® 80960JT Core ■ —Sustained One Instruction/Clock Execution

540L

Contextual Info: 80960RM I/O Processor • Complies with PCI Local Bus Specification, Revision 2.1 ■ 5 K PCI Signalling Environment Data Sheet Advance Information Product Features ■ High Performance 80960JT Core ■ — Sustained One Instruction/Clock Execution — 16 Kbyte, Two-Way Set-Associative

LGA 1155 Socket PIN diagram

Abstract: LGA 1155 PIN diagram LGA 1155 pin out lga1155 pin diagram E3-1275 intel LGA 1155 PIN diagram 1155 PINmap lga1155 land E3-1260L CATERR Catastrophic Error
Contextual Info: Intel Xeon® Processor E3-1200 Family Datasheet, Volume 1 This is Volume 1 of 2 June 2011 Document Number: 324970-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS

MO-47AE

Abstract: ADSP-21060L ADSP-21062L EDI8L32128V EDI8L32512V MPC860 TMS320LC31
Contextual Info: EDI8L32512V White Electronic Designs 512Kx32 SRAM Module.3.3V FEATURES    ADSP-21060L SHARC  ADSP-21062L (SHARC)  Texas Instruments TMS320LC31   The EDI8L32512V is a high speed, 3.3V, 16 megabit SRAM. The device is available with access times of 12, 15, 17 and

100MHZ

Abstract: 133MHZ WED3DL644V
Contextual Info: White Electronic Designs WED3DL644V 4Mx64 SDRAM FEATURES DESCRIPTION The WED3DL644V is a 4Mx64 Synchronous DRAM configured as 4x1Mx64. The SDRAM BGA is constructed with four 4Mx16 SDRAM die mounted on a multi-layer laminate substrate and packaged in a 153 lead, 17mm by

DDR400B

Abstract: HYS64D64020GDL PC2700 PC3200 DDR333 DDR333B DDR400
Contextual Info: D a t a S h e e t , R e v . 1 . 1 , M ay . 2 00 4 HYS64D64020[H/G]DL–5–B HYS64D64020[H/G]DL–6–B 200-Pin Small Outline Dual-In-Line Memory Modules SO-DIMM DDR SDRAM M e m or y P r o du c t s N e v e r s t o p t h i n k i n g . Edition 2004-05 Published by Infineon Technologies AG,

cmo 765

Abstract: GR-78 DDR200 DDR266A PC2100 10292003-DNYO-BD9L infineon ddr numbering
Contextual Info: Data Sheet, Rev. 1.2, Jan. 2004 HYS72D16500GR-[7/8]-A HYS72D32501GR-[7/8]-A Low Profile DDR SDRAM-Modules DDR SDRAM Memory Products N e v e r s t o p t h i n k i n g . The information in this document is subject to change without notice. Edition 2004-06 Published by Infineon Technologies AG,

EDI8L32512V-AC

Abstract: EDI8L32128V EDI8L32512V MO-47AE MPC860 TMS320LC31 ADSP-21060L ADSP-21062L
Contextual Info: White Electronic Designs EDI8L32512V 512Kx32 SRAM Module.3.3V FEATURES DESCRIPTION DSP Memory Solution The EDI8L32512V is a high speed, 3.3V, 16 megabit SRAM. The device is available with access times of 12, 15, 17 and 20ns allowing the creation of a no wait state DSP and RISC

8l32128c

Abstract: block diagram of of TMS320C4X EDI8L32512C20AI EDI8L32512C TMS320C30 TMS320C32 DSP96002 EDI8L24128C EDI8L32256C
Contextual Info: EDI8L32512C 512K x 32 CMOS High Speed Static RAM FEATURES DESCRIPTION DSP Memory Solution • Motorola DSP96002 • Analog SHARC DSP • Texas Instruments TMS320C3x, TMS320C4x Random Access Memory Array • Fast Access Times: 12*, 15, 17, and 20ns • TTL Compatible Inputs and Outputs

Contextual Info: EDI8L32512C ^ E D I 512KX32 SRAM Module ELECTRONIC DESIGNS, INC 512Kx32 CMOS High Speed Static RAM Features DSP Memory Solution The EDI8L32512C is a highspeed, 5V, 16 megabit SRAM. The device is available with access times of 12,15,17 and 20ns allowing the creation of a no wait state DSP memory

Contextual Info: Data Sheet, Rev. 1.3, Nov. 2005 HYS72D32300[G/H]BR–[5/6/7]–C HYS72D64300[G/H]BR–[5/6/7]–C HYS72D64320[G/H]BR–[5/6]–C HYS72D128320[G/H]BR–[6/7]–C 184-Pin Registered Double Data Rate SDRAM Module Reg DIMM DDR SDRAM Memory Products N e v e r s t o p

DDR266A

Abstract: PC2100 PC2100R
Contextual Info: D a t a S h e e t , R e v . 1 . 0 , A p r . 2 00 4 HYS72D16500HR–7–C HYS72D32501HR–7–C 1 8 4 - P i n R eg i s t e r ed D u a l - I n - M e m o r y M o du l e s R D IM M M e m or y P r o du c t s N e v e r s t o p t h i n k i n g . Edition 2004-04 Published by Infineon Technologies AG,

i5336

Contextual Info: Mobile 3rd Generation Intel Core Processor Family Datasheet – Volume 1 of 2 September 2012 Document Number: 326768-004 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS

LHi 968

Abstract: CYNSE70032 CYNSE70128
Contextual Info: CYNSE70128 CYNSE70128 Network Search Engine Cypress Semiconductor Corporation Document #: 38-02040 Rev. *E • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised June 23, 2003 CYNSE70128 CONTENTS 1.0 OVERVIEW . 9

Contextual Info: i PEM 16 M b ASYNC SRAM Mb Austin Semiconductor, Inc. AS8SLC512K32PEC 16Mb, 512Kx32 CMOS 3.3V, High Speed Static RAM Integrated Plastic Encapsulated Microcircuit FEATURES DESCRIPTION „ The AS8SLC512K32 is a high speed, 3.3V, 16Mb SRAM. The device is available with access times of 12, 15, 20

AE31

Abstract: 273328
Contextual Info: 80960RS I/O Processor • ■ Complies with PCI Local Bus Specification, Revision 2.2 Universal 5 V and 3.3 V PCI Signalling Environment (C-stepping only) Data Sheet Advance Information Product Features ■ ■ ■ ■ High Performance 80960JT Core ■ —Sustained One Instruction/Clock Execution

CATERR

Abstract: 1155 PINmap lga115 SBDQ62 LGA 1155 Socket PINmap Platform Environment Control Interface lga1155 land intel LGA 1155 PIN diagram E3-1200 Design for an LGA1155 processor
Contextual Info: Intel Xeon® Processor E3-1200 Family Datasheet, Volume 1 This is Volume 1 of 2 June 2011 Document Number: 324970-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS

LGA 1155 Socket PIN diagram

Abstract: lga1155 cpu socket vid pins location LGA 1155 Socket PIN diagram 3rd i7-2600k intel pch i3-2100 lga 1155 lga1155 MXM 3.0 X8 pinout 1155 PINmap
Contextual Info: 2nd Generation Intel Core Processor Family Desktop and Intel® Pentium® Processor® Family Desktop Datasheet, Volume 1 Supporting Intel® Core™ i7, i5, and i3 Desktop Processor Series Supporting Intel® Pentium® Processor G800 and G600 Series This is Volume 1 of 2

540-lead

Abstract: 273328
Contextual Info: Intel 80960RS I/O Processor • ■ Complies with PCI Local Bus Specification, Revision 2.2 Universal 5 V and 3.3 V PCI Signalling Environment (C-stepping only) Data Sheet Advance Information Product Features ■ ■ ■ ■ High Performance Intel® 80960JT Core