DDRSDRAM Search Results

Contextual Info: Obsolete Device LP2994 LP2994 DDR Termination Regulator Literature Number: SNVS202B March 28, 2011 LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier

LP2995

Abstract: LP2995LQ LP2995M LP2995MR LP2995MRX LP2995MX M08A 3a bus termination regulator psop
Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The

LP2995M

Abstract: c151c LP2995 LP2995LQ LP2995LQX LP2995MR LP2995MRX LP2995MX M08A
Contextual Info: General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The

LP2995

Abstract: LP2995LQ LP2995M LP2995MR LP2995MRX LP2995MX M08A
Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The

MO-224

Abstract: dm311 PC2100 PC2700 MO224 MO-224 thermal
Contextual Info: 256MB, 512MB: x72, ECC, PLL, SR 200-Pin DDR SODIMM Features DDR SDRAM Small-Outline DIMM MT9VDDF3272PH(I) – 256MB, MT9VDDF6472PH(I) – 512MB For component specifications, refer to Micron’s Web site: www.micron.com/products/ddrsdram Features Figure 1:

40b marking

Abstract: PC3200
Contextual Info: 128MB, 256MB, 512MB x64, SR : PC3200 184-Pin DDR UDIMM Features DDR SDRAM Unbuffered DIMM MT8VDDT1664A – 128MB MT8VDDT3264A – 256MB MT8VDDT6464A – 512MB For the component specifications, refer to Micron’s Web site: www.micron.com/products/ddrsdram

LP2995

Abstract: LP2995LQ LP2995M LP2995MR LP2995MRX LP2995MX M08A
Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The

EM488M1644VBA

Contextual Info: 128Mb Mobile SDRAM Ordering Information EM 48 8M 16 4 4 V B A – 75 F EOREX Logo EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM : : : : : : Power Blank : Standard I : Industrial 40 41 42 43 46 48 F: PB free package Density 16M : 16 Mega Bits 8M : 8 Mega Bits

Contextual Info: 1GB, 2GB, 4GB: x72, DR 184-Pin DDR RDIMM Features DDR SDRAM Registered DIMM MT36VDDT12872 – 1GB MT36VDDT25672 – 2GB MT36VDDT51272 – 4GB For component specifications, refer to Micron’s Web site: www.micron.com/products/ddrsdram Features Figure 1:

LP2994

Abstract: LP2994M LP2994MX M08A
Contextual Info: LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier

67512

Abstract: T6N 700 MT46V32M16 MT46V128M4 MT46V64M8 64M8 MT46V64M8 equivalent
Contextual Info: ADVANCE‡ 512Mb: x4, x8, x16 DDR SDRAM DOUBLE DATA RATE DDR SDRAM MT46V128M4 – 32 Meg x 4 x 4 banks MT46V64M8 – 16 Meg x 8 x 4 banks MT46V32M16 – 8 Meg x 16 x 4 banks For the latest data sheet revisions, please refer to the Micron Web site: www.micronsemi.com/datasheets/ddrsdramds.html

TD5860A

Contextual Info: Techcode DATASHEET Source and Sink 1.5A/2A Fast Transient Response Line Regulator TD5860 A General Description Features The TD5860/TD5860A linear regulator is designed to provide a regulated voltage with bi-direction output current for DDRSDRAM termination voltage. The

Contextual Info: RT9005A/B Preliminary DDR VDDQ and Termination Voltage Regulator General Description Features The RT9005A/B is a dual-output linear regulator for DDRSDRAM VDDQ supply and termination voltage VTT supply. z The Regulator is capable of actively sinking or sourcing

MAS 10 RCD

Abstract: AD404M42VSA-5 AD404M42VSA-6 AD404M42VTA-5 AD404M42VTA-6 ASCEND Semiconductor
Contextual Info: ASCEND Semiconductor 4Mx4 EDO Data sheet Rev.1 Page 1 AD 40 4M 4 2 V S A – 5 Ascend Semiconductor EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM : : : : : : 40 41 42 43 46 48 Density 16M : 16 Mega Bits 8M : 8 Mega Bits 4M : 4 Mega Bits 2M : 2 Mega Bits 1M : 1 Mega Bit

psop-8

Abstract: 8 lead psop-8 NS package num. mra08a resistor 0,15 Ohm 5W DATA SHEET psop 44 northbridge Op amp circuit applications SSTL-2 5041c free circuit diagram of motherboard SO-8
Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The

LP2995

Abstract: LP2995LQ LP2995LQX LP2995M LP2995MR LP2995MRX LP2995MX M08A
Contextual Info: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The

EM481M1622VTA

Contextual Info: 16Mb SDRAM Ordering Information EM 48 1M 16 2 2 V T A – 6 L EOREX Memory EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM : : : : : : Power Blank : Standard L : Low power I : Industrial 40 41 42 43 46 48 F: PB free package Density 16M : 16 Mega Bits 8M : 8 Mega Bits

Contextual Info: LP2994 LP2994 DDR Termination Regulator Literature Number: SNVS202B LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier

LP2994

Abstract: LP2994M LP2994MX M08A
Contextual Info: LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier

EM482M3244VTA

Contextual Info: 64Mb SDRAM Ordering Information EM 48 2M 32 4 4 V T A – 5 L EOREX Logo EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM : : : : : : F: PB free package Power Blank : Standard L : Low power I : Industrial 40 41 42 43 46 48 Density 16M : 16 Mega Bits 8M : 8 Mega Bits

Contextual Info: 512Mb: x4, x8, x16 DDR SDRAM Features Double Data Rate DDR SDRAM MT46V128M4 – 32 Meg x 4 x 4 banks MT46V64M8 – 16 Meg x 8 x 4 banks MT46V32M16 – 8 Meg x 16 x 4 banks For the latest data sheet, refer to Micron’s Web site: www.micron.com/ddrsdram Features

T6N 700

Abstract: bl p65 DDR200 DDR266A DDR266B
Contextual Info: 64Mb: x4, x8, x16 DDR SDRAM MT46V16M4 – 4 Meg x 4 x 4 banks MT46V8M8 – 2 Meg x 8 x 4 banks MT46V4M16 – 1 Meg x 16 x 4 banks DOUBLE DATA RATE DDR SDRAM For the latest data sheet revisions, please refer to the Micron Web site: www.micronsemi.com/datasheets/ddrsdramds.html

LP2995M

Abstract: LP2995MRX LP2995MX M08A LP2995 LP2995LQ LP2995LQX LP2995MR PSOP8
Contextual Info: General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The

2N7002

Abstract: Eletrolytic capacitor
Contextual Info: RT9005A/B DDR VDDQ and Termination Voltage Regulator General Description Features The RT9005A/B is a dual-output linear regulator for DDRSDRAM VDDQ supply and termination voltage VTT supply. z The Regulator is capable of actively sinking or sourcing up to 2A. The output termination voltage can be tightly