D8D15 Search Results

Contextual Info: S N 74AC T215 7 2K x 16 C A C H E A D D R E S S C O M PA R A TO R /D A TA RAM D3326, JANUARY 1990-REVlSED JUNE 1990 Fast A ddress to Match Delay . . . 20 ns Max FN PACKAGE TOP VIEW Totem -Pole and Open-Drain Match Outputs On-Chip Address/D ata Com parator

TMS320D

Abstract: dpdi EC K2U 74299 TMS320C30 EF vs EC LS74
Contextual Info: TLC32044C, TLC32044I VOICE BAND ANALOG INTERFACE CIRCUITS D3098, MARCH 1988-REV ISED DECEMBER 1990 Advanced LinCMOS Silicon-Gate Process Technology N PA C KA G E T O P V IE W NU C 1 ^ 2 8 D n u RESET C 2 27 U n u EODR C 3 26 J I N FSR C 4 24 D A U X IN +

TC55188

Abstract: TC55188T-25 TC55188T-20 TC55188T
Contextual Info: •»ilK 2 - W A Y 4,096 W ORDS x 18 BITS/8,192 WORDS x 18 BITS CMOS STATIC CACHE DATA RAM DESCRIPTION The TC55188T is a 147,456bits high-speed static RAM which can be user-configured either a s 2-way 4,096 words by 18 bits or as 8,192 words by 18 bits. It is provided with a byte control, on-chip

SPW 12w

Abstract: TMS380c16 RRU 32
Contextual Info: TMS380C26 NETWORK COMMPROCESSOR SPW S010A -APRIL 1992- R E V IS E D MARCH 1993 I • IEEE 802.5 and IBM Token-Ring Network Compatible • Low-Cost Host-Slave I/O Interface Option • IEEE 802.3 and Blue Book Ethernet™ Network Compatible • Selectable Host System-Bus Options

m1 250c fuse

Abstract: at32uc3c em 234 stepper dtx 370 DTH block diagram lta 301 VT 546 Modem basic circuit diagram EIC 4021 shift registers 4050
Contextual Info: Features • High Performance, Low Power 32-bit AVR Microcontroller – – – – • • • • • • • • • • • • Compact Single-cycle RISC Instruction Set Including DSP Instruction Set Built-in Floating-Point Processing Unit FPU Read-Modify-Write Instructions and Atomic Bit Manipulation

AT91SAM3U4

Abstract: at91sam3 1N1308 MAR 735 REGULATOR IC 7912 pin identify AT91SAM3U4E SAM3u1 AT91SAM3U 3961 G.E 0x20180
Contextual Info: Features • Core • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 96 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,

32176 Group PWM CODE

Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

Contextual Info: M2S1G64CBH4B5P / M2S2G64CB88B5N / M2S4G64CB8HB5N 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 / PC3-12800 Unbuffered DDR3 SO-DIMM Based on DDR3-1066/1333/1600 128Mx16 1GB / 256Mx8 (2GB) / 256Mx8 (4GB) SDRAM B-Die Features •Performance:

HIP-66

Contextual Info: FLASH AS8FLC1M32 FIGURE 1: PIN ASSIGNMENT Top View Hermetic, Multi-Chip Module (MCM) 32Mb, 1M x 32, 3.0Volt Boot Block FLASH Array Available via Applicable Specifications: • MIL-PRF-38534, Class H FEATURES • • • • • • • • • • • •

PIC16F LED matrix

Abstract: pic18f MCU Family Reference Manual DS51833 PIC16 example asm i2c slave PIC16F1937 PIC24f example code CTMU capacitive touch PIC16F PIC32MX7* reference manual DS51865 PIC18F example code i2c
Contextual Info: mTouch Advanced Capacitive Evaluation Kits User’s Guide 2010 Microchip Technology Inc. DS41385C Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet.

GCM 38112

Abstract: Wifi to I2C ST ATUC3A4256S AT32UC3A3 dsp ssb modulation demodulation barcode reader using avr AT32UC3A64 ATUC3A3256 DesignWare Hi-Speed USB On-The-Go Controller AT32UC3A3256S
Contextual Info: Features • High Performance, Low Power 32-bit AVR Microcontroller • • • • • • • • • • • • – Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation

Contextual Info: 32bit TX System RISC TX19 family TMP1942FDU/XBG Rev1.0 March 29, 2007 TMP1942FD 32-Bit RISC Microprocessor TX19 Family TMP1942FDU/FDXBG 1. Features The TX19 is a family of high-performance 32-bit microprocessors that offers the speed of a 32-bit RISC solution with the added advantage of a significantly reduced code size of a 16-bit architecture.

82C452

Abstract: P82C452 82C452A crt controller 6845 MCA Bus 8bit vga controller plasma 640x480 64kx4 DRAM LM339 XR31
Contextual Info: 82C452 Super VGA Graphics Controller Data Sheet September 1991 P R E L I M I N A R Y Copyright Notice Copyright 1990, Chips and Technologies, Inc. ALL RIGHTS RESERVED. This manual is copyrighted by Chips and Technologies, Inc. You may not reproduce,

siemens sab 82532

Abstract: 82258 SA 82532 SAB 80286 csc 2323 sab80286 STT 3 SIEMENS 80286 microprocessor pin out diagram ESCC2 siemens sab 82525
Contextual Info: SIEM ENS Enhanced Serial Communication Controller ESCC2 SAB 82532 Preliminary Data 1.1 CMOS 1C General Features S erial Interface • Two independent full duplex serial channels - On chip clock generation or external clock source - On chip DPLL for clock recovery of each

msi motherboard circuit diagram

Abstract: intel 82230 ZyMOS 82231 intel PC MOTHERBOARD CIRCUIT diagram SA12 SA13 SA15 82230 82231
Contextual Info: P R Ii y it f lO IM ß W in t é T 82232 VERY HIGH INTEGRATION/PC-AT* SYSTEM BUFFERS Fully IBM PC-AT and 82230/82231 Compatible Two Chips Replace Most Address and Data Buffers on the PC-AT Motherboard One Chip Type Supports Both Address and Data Buffer Applications. Controls

EPROM 271024

Abstract: 271024 274096 271024 eprom 272048 EPROM 272048 16KX8 27040 EPROM 27020 27C512
Contextual Info: EconoROM II User’s Manual Version 1.1 Covers Models ER2-256,ER2-512,ER2-1M,ER2-2M,ER2-4M, ER2-220 and ER2-240 Copyright 1996, 1997 by TechTools, all rights reserved Table of Contents Introduction . 1

DFSDM

Abstract: SAM9M10 K 2141 AC97 ARM926EJ-S AT91SAM ISO7816 NBC 3111 hc 541 rfid reader id-20
Contextual Info: Features • 400 MHz ARM926EJ-S ARM Thumb® Processor – 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU • Memories • • • • – DDR2 Controller 4-bank DDR2/LPDDR, SDR/LPSDR – External Bus Interface supporting 4-bank DDR2/LPDDR, SDR/LPSDR, Static

AMD Series D flash memory card

Contextual Info: AMDËI AmCOOXCFLKA 1,2, or 4 Megabyte 5.0 Volt-only “C-Series” Flash Memory PC Card DISTINCTIVE CHARACTERISTICS • High performance — 150 ns maximum access time ■ Single supply operation — 5.0 V ± 5% for read, write and erase ■ CMOS low power consumption

Contextual Info: CONDENSED AMD£I AmMCLOOXA 2 or 4 Megabyte 3.0 Volt-only Flash Miniature Card DISTINCTIVE CHARACTERISTICS • 2 or 4 Mbytes of addressable Flash memory ■ 2.7 V to 3.6 V, single power supply operation — Write and read voltage: 3.0 V -10/+20% — No additional supply current required for VPP

R14 P1F

Abstract: N-333 PP7F 1BE3 P53 transistor A1-U1-U17-A17 3LH30 zz12
Contextual Info: TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 Series TMP92CF26AXBG Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. TMP92CF26A

tms 3617

Abstract: TMS 3511 NS TMP1962F-10
Contextual Info: TMP1962F10AXBG 32-Bit RISC Microprocessor TX19 Family TMP1962F10AXBG 1. Features The TX19 is a family of high-performance 32-bit microprocessors that offers the speed of a 32-bit RISC solution with the added advantage of a significantly reduced code size of a 16-bit architecture. The instruction set

TLCS-68000

Contextual Info: TOSHIBA TMP68000 / 68HC000 5. PROCESSING STATES This section describes the actions of the TM P68000 which are outside the norm al processing associated w ith the execution of instructions. The functions of the bits in the supervisor portion of the status register are covered: the supervisor/user bit, the trace

CD 2399 GP

Abstract: 80387 DX Users Manual Programmers Reference
Contextual Info: PRByBJOODOÂIfflr in t e i Intel486 DX MICROPROCESSOR 168-Pin Grid Array Package High Performance Design — RISC Integer Core with Frequent Instructions Executing in One Clock — 25 MHz, 33 MHz, and 50 MHz Clock — 80, 106, 160 Mbyte/sec Burst Bus — CHMOS IV and CHMOS V Process

Contextual Info: IB M 1 1 M 4 6 4 0 C IB M 1 1 M 4 6 4 0 C B 4M X 64 DRAM MODULE • Au contacts • Optimized for byte-write non-parity applications Features • 168 Pin JEDEC Standard, 8 Byte Dual In-line Memory Module • System Performance Benefits: - • 4Mx64 Fast Page Mode DIMM