CK 2T Search Results

74F420

Abstract: F420 D2939
Contextual Info: 420 54F/74F420 C o nn ectio n Diagram s Parallel Check Bit/Syndrome Bit Generator a lle i ch e ck bit/syndrom e bit generator. The ’ F420 ming code to generate 7 ch e ck bits from a 32-bit en operated in the ch e ck bit generate mode. When romjfffjjftosrate mode, the ch e ck bits and data bits

CK-408

Abstract: CY28322-2 CK-408 CK-Titan Clock Synthesizer G2021
Contextual Info: PRELIMINARY CY28322-2 133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs Features Benefits  • Compliant with Intel CK-Titan and CK-408 clock synthesizer/driver specifications Supports next generation Pentium processors using differential clock drivers

UFG-C1

Abstract: CK-408 CY28322-2
Contextual Info: PRELIMINARY CY28322-2 133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs Features Benefits  • Compliant with Intel CK-Titan and CK-408 clock synthesizer/driver specifications Supports next generation Pentium processors using differential clock drivers

EM44AM1684LBA

Abstract: DDR2-667 EM44AM1684LBA-37F EM44AM1684LBA-3F EM44AM1684LBA-5F emrs3
Contextual Info: eorex EM44AM1684LBA 256Mb 4Mx4Bank×16 Double DATA RATE 2 SDRAM Features Description • JEDEC Standard VDD/VDDQ=1.8V ± 0.1V. • All inputs and outputs are compatible with SSTL_18 interface. • Fully differential clock inputs (CK,/CK) operation. • 4 Banks

DDR2-667

Abstract: DDR2-800MHZ
Contextual Info: eorex EM44CM1688LBA 1Gb 8Mx8Bank×16 Double DATA RATE 2 SDRAM Features Description • JEDEC Standard VDD/VDDQ=1.8V ± 0.1V. • All inputs and outputs are compatible with SSTL_18 interface. • Fully differential clock inputs (CK,/CK) operation. • 8 Banks

NT5CB64M16AP-BE

Contextual Info: NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP 1Gb DDR3 SDRAM A-Die Features • VDD=VDDQ=1.5V ± 0.075V JEDEC Standard Power Supply • Write Leveling • OCD Calibration • 8 internal banks (BA0 - BA2) • Dynamic ODT (Rtt_Nom & Rtt_WR) • Differential clock inputs (CK, CK)

DDR2-667

Abstract: EM44AM1684LBC EM44AM1684LBC-37F EM44AM1684LBC-3F EM44AM1684LBC-5F BGA84
Contextual Info: eorex EM44AM1684LBC 256Mb 4Mx4Bank×16 Double DATA RATE 2 SDRAM Features Description • JEDEC Standard VDD/VDDQ=1.8V ± 0.1V. • All inputs and outputs are compatible with SSTL_18 interface. • Fully differential clock inputs (CK,/CK) operation. • 4 Banks

EM44BM1684LBA

Abstract: bga 84 BGA84 BGA-84 DDR2-667 em44bm1684lba-3f
Contextual Info: eorex EM44BM1684LBA 512Mb 8Mx4Bank×16 Double DATA RATE 2 SDRAM Features Description • JEDEC Standard VDD/VDDQ=1.8V ± 0.1V. • All inputs and outputs are compatible with SSTL_18 interface. • Fully differential clock inputs (CK,/CK) operation. • 4 Banks

Contextual Info: 256Mb LPDDR SDRAM NT6DM16M16AD / NT6DM8M32AC Options Feature  Double-data rate architecture; two data transfer per clock cycle  Bidirectional, data strobe DQS is transmitted/received with data, to be used in capturing data at the receiver  Differential clock inputs (CK and /CK)

EM658160TS-4

Abstract: EM658160 EM658160TS-5 e-tron
Contextual Info: EtronTech EM658160 4M x 16 DDR Synchronous DRAM SDRAM Etron Confidential (Rev. 1.1 Jan./2002) Features Pin Assignment (Top View) • • • • • • • • Fast clock rate: 300/285/250/200/166/143/125MHz Differential Clock CK & /CK Bi-directional DQS

K4X51163PE-L(F)E/GC6

Abstract: k4x51163pe K4X51163PE-L SEC k4x samsung CL21 CL21 CL31 DDR266 DDR333
Contextual Info: K4X51163PE - L F E/G Mobile DDR SDRAM 32Mx16 Mobile DDR SDRAM 1. FEATURES • VDD/VDDQ = 1.8V/1.8V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK)

EM6AA320BI-5

Abstract: Etron ba1s EM6AA320BI-4 BA1 K11
Contextual Info: EtronTech EM6AA320 8M x 32 DDR SDRAM Etron Confidential Preliminary Rev 0.0 7/2002 Features Overview • Fast clock rate: 300/285/250/200 MHz • Differential Clock CK & CK# input The EM6AA320 DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 256

K4M56163PI

Abstract: DDR266 DDR333 60FBGA SDRAM16MX16
Contextual Info: K4X56163PI - L F E/G Mobile DDR SDRAM 16Mx16 Mobile DDR SDRAM 1. FEATURES • VDD/VDDQ = 1.8V/1.8V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK)

samsung CL21

Abstract: K4X56323PI K4X56323 CL21 DDR266 DDR333
Contextual Info: K4X56323PI - 7 8 E/G Mobile DDR SDRAM 8M x32 Mobile DDR SDRAM 1. FEATURES • VDD/VDDQ = 1.8V/1.8V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK)

K4X1G163PC-L

Abstract: 60-FBGA samsung CL21 DDR266 DDR333 mobile ddr 64mx16 k4x1g163pc-xxxx
Contextual Info: K4X1G163PC - L F E/G Mobile DDR SDRAM 64Mx16 Mobile DDR SDRAM 1. FEATURES • VDD/VDDQ = 1.8V/1.8V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK)

Contextual Info: ESM T M15F2G16128A DDR III SDRAM 16M x 16 Bit x 8 Banks DDR III SDRAM Feature 1.5V ± 0.075V JEDEC Standard Power Supply Output Driver Impedance Control 8 Internal memory banks (BA0- BA2) Differential bidirectional data strobe through ZQ pin Differential clock input (CK, CK )

Contextual Info: CY28344 FTG for Intel Pentium 4 CPU and Chipsets Features • Compatible to Intel CK-Titan and CK-408 Clock Synthesizer/Driver Specifications • System frequency synthesizer for Intel Brookdale 845 and Brookdale G Pentium® 4 Chipsets • Programmable clock output frequency with less than

48MHZ

Abstract: CK-408 CY28344 SSOP-48
Contextual Info: CY28344 FTG for Intel Pentium 4 CPU and Chipsets Features • Compatible to Intel CK-Titan and CK-408 Clock Synthesizer/Driver Specifications • System frequency synthesizer for Intel Brookdale 845 and Brookdale G Pentium® 4 Chipsets • Programmable clock output frequency with less than

EM6A9320

Abstract: EM6A9320BI-4 EM6A9320BI-5 BA1l4
Contextual Info: EtronTech EM6A9320 4M x 32 DDR SDRAM Preliminary Rev 0.6 5/2006 Features Overview • Fast clock rate: 350/333/300/285/250/200 MHz • Differential Clock CK & CK# input The EM6A9320 DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 128

samsung CL21

Abstract: K4X51323PE CL21 CL31 DDR266 DDR333
Contextual Info: K4X51323PE - 7 8 E/G Mobile DDR SDRAM 16Mx32 Mobile DDR SDRAM 1. FEATURES • VDD/VDDQ = 1.8V/1.8V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK)

DDR222

Abstract: DDR266 K4X56323PG
Contextual Info: K4X56323PG - 7 8 E/G Mobile-DDR SDRAM 8M x32 Mobile-DDR SDRAM FEATURES • 1.8V power supply, 1.8V I/O power • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK)

Contextual Info: NT2GT64U8HB0JY 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM 240pin Unbuffered DDR2 SDRAM MODULE Based on 128Mx8 DDR2 SDRAM B-die Features Performance: PC2-4200 PC2-5300 PC2-6400 -37B -3C -25D 4 5 6 f CK Clock Frequency 266 333 400 t CK Clock Cycle 3.75 3 2.5

4mx32

Abstract: ba1s EM6A9320BI-4 EM6A9320BI-5 etron 4mx32 Etron Technology EM6A9320
Contextual Info: EtronTech EM6A9320 4M x 32 DDR SDRAM Etron Confidential Preliminary Rev 0.3 7/2002 Features Overview • Fast clock rate: 350/333/300/285/250/200 MHz • Differential Clock CK & CK# input The EM6A9320 DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 128

48MHZ

Abstract: CK-408 CY28344 SSOP-48
Contextual Info: CY28344 PRELIMINARY FTG for Intel Pentium 4 CPU and Chipsets Features • Compatible to Intel CK-Titan and CK-408 Clock Synthesizer/Driver Specifications • System frequency synthesizer for Intel Brookdale 845 and Brookdale G Pentium® 4 Chipsets • Programmable clock output frequency with less than