CK 2T Search Results

74F420

Abstract: F420 D2939
Contextual Info: 420 54F/74F420 C o nn ectio n Diagram s Parallel Check Bit/Syndrome Bit Generator a lle i ch e ck bit/syndrom e bit generator. The ’ F420 ming code to generate 7 ch e ck bits from a 32-bit en operated in the ch e ck bit generate mode. When romjfffjjftosrate mode, the ch e ck bits and data bits

CK-408

Abstract: CY28322-2 CK-408 CK-Titan Clock Synthesizer G2021
Contextual Info: PRELIMINARY CY28322-2 133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs Features Benefits  • Compliant with Intel CK-Titan and CK-408 clock synthesizer/driver specifications Supports next generation Pentium processors using differential clock drivers

NT5CB64M16AP-BE

Contextual Info: NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP 1Gb DDR3 SDRAM A-Die Features • VDD=VDDQ=1.5V ± 0.075V JEDEC Standard Power Supply • Write Leveling • OCD Calibration • 8 internal banks (BA0 - BA2) • Dynamic ODT (Rtt_Nom & Rtt_WR) • Differential clock inputs (CK, CK)

DDR2-667

Abstract: EM44AM1684LBC EM44AM1684LBC-37F EM44AM1684LBC-3F EM44AM1684LBC-5F BGA84
Contextual Info: eorex EM44AM1684LBC 256Mb 4Mx4Bank×16 Double DATA RATE 2 SDRAM Features Description • JEDEC Standard VDD/VDDQ=1.8V ± 0.1V. • All inputs and outputs are compatible with SSTL_18 interface. • Fully differential clock inputs (CK,/CK) operation. • 4 Banks

samsung CL21

Abstract: K4X1G323PC K4X1G323PC-7 K4X1G323 CL21 CL31 DDR266 DDR333 row decoder
Contextual Info: K4X1G323PC - L F E/G Mobile DDR SDRAM 32Mx32 Mobile DDR SDRAM 1. FEATURES • VDD/VDDQ = 1.8V/1.8V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK)

K4X1G163PC-L

Abstract: 60-FBGA samsung CL21 DDR266 DDR333 mobile ddr 64mx16 k4x1g163pc-xxxx
Contextual Info: K4X1G163PC - L F E/G Mobile DDR SDRAM 64Mx16 Mobile DDR SDRAM 1. FEATURES • VDD/VDDQ = 1.8V/1.8V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK)

Contextual Info: ESM T M15F2G16128A DDR III SDRAM 16M x 16 Bit x 8 Banks DDR III SDRAM Feature 1.5V ± 0.075V JEDEC Standard Power Supply Output Driver Impedance Control 8 Internal memory banks (BA0- BA2) Differential bidirectional data strobe through ZQ pin Differential clock input (CK, CK )

samsung CL21

Abstract: K4X51323PE CL21 CL31 DDR266 DDR333
Contextual Info: K4X51323PE - 7 8 E/G Mobile DDR SDRAM 16Mx32 Mobile DDR SDRAM 1. FEATURES • VDD/VDDQ = 1.8V/1.8V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK)

DDR222

Abstract: DDR266 K4X56323PG
Contextual Info: K4X56323PG - 7 8 E/G Mobile-DDR SDRAM 8M x32 Mobile-DDR SDRAM FEATURES • 1.8V power supply, 1.8V I/O power • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK)

NT2GT64U8HB0JY

Contextual Info: NT2GT64U8HB0JY 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM 240pin Unbuffered DDR2 SDRAM MODULE with ECC Based on 128Mx8 DDR2 SDRAM B-die Features Performance: PC2-4200 PC2-5300 PC2-6400 -37B -3C -25C 4 5 5 f CK Clock Frequency 266 333 400 t CK Clock Cycle 3.75

Contextual Info: NT2GT64U8HB0JY 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM 240pin Unbuffered DDR2 SDRAM MODULE with ECC Based on 128Mx8 DDR2 SDRAM B-die Features Performance: PC2-4200 PC2-5300 PC2-6400 -37B -3C -25C 4 5 5 f CK Clock Frequency 266 333 400 t CK Clock Cycle 3.75

NT2GT64U8HB0JY-3C

Abstract: NT2GT64U8HB0JY-25D DDR2 DIMM 240 pinout PC2-5300 PC2-6400 SSTL-18 NT2GT64U8HB0JY
Contextual Info: NT2GT64U8HB0JY 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM 240pin Unbuffered DDR2 SDRAM MODULE Based on 128Mx8 DDR2 SDRAM B-die Features Performance: PC2-4200 PC2-5300 PC2-6400 -37B -3C -25D 4 5 6 f CK Clock Frequency 266 333 400 t CK Clock Cycle 3.75 3 2.5

Contextual Info: TOSHIBA TMPA8701 CH/CK/CM CMOS 8 -Bit Microcontroller TMPA8701CHN/F, TMPA8701CKN/F, TMPA8701CMN/F The A8701CH/CK/CM is the high speed and high performance 8 bit single chip microcomputer. This MCU contains CPU core, ROM, RAM, input / output ports, six multi-function timer / counter, serial interface, on­

Contextual Info: NT2GT72U8PB0JY 2GB: 256M x 72 Unbuffered DDR2 SDRAM DIMM with ECC 240pin Unbuffered DDR2 SDRAM MODULE with ECC Based on 128Mx8 DDR2 SDRAM B-die Features Performance: PC2-4200 PC2-5300 PC2-6400 -37B -3C -25D 4 5 6 f CK Clock Frequency 266 333 400 t CK Clock Cycle

NT2GT72U8PB0JY-3C

Abstract: DDR2 DIMM 240 pinout PC2-5300 PC2-6400 SSTL-18 NT2GT72U8PB0JY-25D
Contextual Info: NT2GT72U8PB0JY 2GB: 256M x 72 Unbuffered DDR2 SDRAM DIMM with ECC 240pin Unbuffered DDR2 SDRAM MODULE with ECC Based on 128Mx8 DDR2 SDRAM B-die Features Performance: PC2-4200 PC2-5300 PC2-6400 -37B -3C -25D 4 5 6 f CK Clock Frequency 266 333 400 t CK Clock Cycle

74374

Abstract: 74574 HCT 74576 74575 ALSB76 74576
Contextual Info: - 74576 263- Octal 3-State D-FFs Inverted Vcc Q0 5T Iff Q3 5? Q5 Q6 T37 CLO CK J 2 o1 4 T # 1 J 7 7 | J 7 7 1 ^ ^ 7 1 ,i J o e 3 OE Q O E Q OE 3 OE 1 d c,k d c.k 1 ! L L m n L 01 01 PTPOT DO (3JNTRCC q CK dck 1 r u 02 | m 03 CaK I I I 1 i OE Q OE Q OE .CK

8086 logic diagram

Abstract: generated csync 1j05 82730
Contextual Info: intel 82285 CLOCK GENERATOR AND READY INTERFACE FOR I/O COPROCESSORS 82285 is an 18 pin bipolar clo ck genera to r/d rive r designed to provide clo ck signals fo r the 82730,82586, or oth er master peripherals. It also contains READY m ultiplexing logic to provide the required RDYO and

ba1s

Abstract: 8Mx32 EM6AA320BI-5MSG EM6AA320BI-5MS
Contextual Info: EtronTech EM6AA320 8M x 32 DDR SDRAM Preliminary Rev 0.4 June/2007 Features Overview • Fast clock rate: 200 MHz • Differential Clock CK & CK# input The EM6AA320 DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 256 Mbits. It is internally configured as a quad 2M x 32

A8701

Abstract: RJP 30 h1 SCL 4011 BC SJ 76 TVS dIODE TMPA8701 BLF 278 ISA on-off valve OC23 p64s TMPA8701CHF
Contextual Info: TOSHIBA TMPA8701 CH/CK/CM CMOS 8-Bit M icrocontroller TMPA8701CHN/F, TMPA8701CKN/F, TMPA8701CMN/F The A8701CH/CK/CM is the high speed and high performance 8 b it single chip m icrocom puter. This MCU contains CPU core, ROM, RAM, in p u t / o u tp u t ports, six m u lti-function tim e r / counter, serial interface, o n ­

command cathode 7 SEGMENT DISPLAY LT 543

Abstract: ic cd 4015 7 SEGMENT DISPLAY COMMON CATHODE lt 543 8700c ic cd 4017 BLF 272 common cathode 7 SEGMENT DISPLAY LT 543 te 4017 TLCS-870
Contextual Info: TOSHIBA TMPA8700CH/CK/CM/CP/CS CMOS 8 -Bit M icrocontroller TMPA8700CHN/F, TMPA8700CKN/F, TMPA8700CMN/F, TMPA8700CPN/F, TMPA8700CSN/F The A8700CH/CK/CM/CP/CS is the high speed and high perform ance 8 b it single chip m icrocom puter. This MCU contains CPU core, ROM, RAM, in p u t / o u tp u t ports, six m u lti-function tim e r / counter, serial interface,

Contextual Info: CDC391 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS SCAS334A - DECEMBER 1992 - REVISED NOVEMBER 1995 D PACKAGE TOP VIEW L ow O utp ut S k e w fo r C lo ck-D istrlbu tio n a nd C lo ck-G en eratlo n A p plicatio ns T T L -C o m p a tlb le In p u ts and O utputs

MG40S2YK1

Abstract: MG30G2CL3 MG25M2CK2 MG50M2YK9 MG50M2CK2 MG50G2CL3 MG25M2YK9 TA8250 MG15N2YK1 MG25M2YK1
Contextual Info: - 218 — n p n o 9 - ' y \ v • o y : i - * 'í ) l - f ''í ± - F i 4 Vauxnv , > - i n « 2 flü ü fflü g tl) a s n o s CK-1 /'WW^UKU.lui.t CK-2 tu o ¡> j± o Y - V T o BI y h / H 1’ c r ) i¡'± / \ Z B1 aZ E l/ B2 32 í± 1 . T c=25 c * V CBO

Biphase

Abstract: 16C50 z16c50
Contextual Info: PRELIMINARY PRODUCT SPECIFICA TION Z16C50 D D P L L D u a l D ig it a l P h a s e L o c k e d L o o p M ic r o c o n t r o l l e r FEATURES • Two independent D igital Phase Locked Loops in one package. ■ 10 MHz and 20 M Hz C lock operation ■ Selectable clo ck rate, c lo ck sam pling edge, and data

MG30G2CL3

Abstract: MG50M2CK2 MG75H2CL1 MG25M2CK2 MG50M2YK9 MG75H2YL1A MG50G2YL1A MG25M2YK9 MG50Q2Y MG15N2YK1
Contextual Info: - 218 — n p n , > o 9 - ' y \ v • o y : i- * 'í) l- f ''í± - F i4 Vauxnv - i n « 2 flü ü fflü g tl) asn o s CK-1 / 'W W ^ U K U . lu i. t CK-2 tu o ¡>j± o Y - V T o BI y h / H 1’ c r ) i¡'±/\ Z B1 aZ E l/ B2 32 í± 1 . T c=25 c * m % V CBO