CC02V Search Results

Contextual Info: PRELIM INARY- - October 1995 Edition 2.1 = FUJITSU PRODUCT PROFILE SHEET MB8 117805A-60/-70 CMOS 2M X 8BIT HYPER PAGE MODE DYNAMIC RAM CM O S 2,097,152x 8B IT Hyper Page Mode Dynam ic RAM The Fujitsu MB8117805A is a fully decoded CMOS Dynamic RAM DRAM that contains

S-22

Abstract: S-22H S-22H10 S-22H12 S-22S S-22S10 S-22S12 X2210 X2212
Contextual Info: Coritents Features . 1 Pin Assignm ent. Block Diagram . 1 2 Absolute Maximum Ratings 2 . Recom m ended Operating Conditions

34-PIN

Abstract: DS1643 DS1643P DS164XP DS9034PCX nv ram 8kx8
Contextual Info: DS 1643/DS 1643 P -70 /1 00 PRELIMINARY DALLAS SEMICONDUCTOR DS1643/DS1643P -70/100 Nonvolatile Timekeeping RAM FEATURES PIN ASSIGNMENT • Integrated NV SRAM, real tim e clock, crystal, p o w e rfail control circuit and lithium energy source • C lock registers are accessed identical to the static

1J28K

Contextual Info: MOSEL- VITEUC MS621008 128K x 8 CMOS STATIC RAM Features • Fast Access Times: 20/25/35 ns ■ High Density 400-Mil SOJ Package ■ Low Standby Power ■ TTL Compatible I/O ■ 5V + 10% Supply ■ Fully Static Operation ■ Three State Output ■ JEDEC Standard Pinout

HM6207

Abstract: HM6207P HM6207LP45 HM6207LP-45
Contextual Info: HM6207 Series 262144-word x 1-bit High Speed CMOS Static RAM The Hitachi H M 6 2 0 7 is a high speed 2 5 6 k static R A M organized as 2 5 6 -k w ord x 1-bit. It realizes high speed a cce ss time 35/45 nsl and low power consumption, employing the advanced

S9034PCX

Contextual Info: DS 1743/D S1743P PRELIMINARY DALLAS s e m ic o n d u c to r _ DS1743/DS1743P Y2KC Nonvolatile Timekeeping RAM PIN ASSIGNMENT FEATURES • Integrated NV SRAM, real tim e clock, crystal, powerfail control circuit and lithium energy source NC A12 A7 A6 A5

Contextual Info: » « Y I I H D W I HYM532810A M-Series 8Mx32-blt CMOS DRAM MODULE DESCRIPTION The HYM532810A is a 8M x 32-bit Fast page mode CMOS DRAM module consisting of sixteen HY5117400A in 24/26 pin SQJ or TSOPfl on a 72 pin glass-epoxy printed circuit board. 0.22nF decoupling

d114

Abstract: EDH84H64C-35CC EDH84H64C-55CC t-46-23-10
Contextual Info: ELECTRO NIC DESIGNS INC AS D E | 353011M □0000^3 0 | •' T -4 6 -2 3 -1 0 EDH 84H64C The fu tu r e . . . 35/45/55/70 Module to d a y .i PRELIMINARY 64Kx4 SRAM CMOS, High Speed Features The EDH 84H64C provides 64Kx4 of fully static, CMOS memory in a single, compact package.

SBC20

Contextual Info: KM44C4100L CMOS DRAM 4 M X 4 Bit CMOS Dynamic RAM with Fast Page Mode FEATURES GENERAL DESCRIPTION • Performance range: The Samsung KM44C4100L is a CMOS high speed 4,194,304 x 4 Dynamic Random Access Memory. Its de­ sign is optimized for high performance applications

Contextual Info: BiCMOS SRAM KM64B1003 262,144 WORD x 4 Bit With OE Ultra High-Speed BiCMOS Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Time: 8, 10, 12, 15ns (Max.) • Low Power Dissipation Standby (TTL) : 60mA (Max.) (CM O S): 10mA (Max.) Operating : KM6481003J-8: 165mA (Max.)

Contextual Info: - PRELIMINARYApril 1996 Edition 2.2 _ PRODUCT PROFILE SHEET - C P - FUJITSU MB81V17800A-60/-70 CMOS 2M X 8BIT FAST PAGE MODE DYNAMIC RAM CMOS 2,097,152 x 8BIT Fast Page Mode Dynamic RAM The Fujitsu MB81V17800A is a fully decoded CMOS Dynamic RAM DRAM that contains

asus schematic diagram

Abstract: asus f3 asus 74MC14 Asus P5 FJ 3528 asus block diagram asus diagram asus a6 EL B17 A017
Contextual Info: SLK BLOCK DIAGRAM V 2.00 < INTEL COPPERMINE GCL I N V ,LCD SBT OZ998 1,2,3 37 38 HOST BUS MEM BUS INTEL ON BOARD 64MB SDRAM CLOCKS 9248-10 1 c* CO I/O BOARD IC S SODIMM ONE SLOT 11 PCI BUS 10 USB P O R T *2 RJ-11 CARDBUS CONTREOLLER « I 1451 W 1 8 ,1 9 R J -4 5

GM76C88L-15

Abstract: STATIC RAM 16x8 GM76C88L15
Contextual Info: GOLDSTAR TECHNOLOGY I N C / 47E D 405Ô7S7 D D0 35 73 3 I GST GoldStar GM76C88L 8,192 WORDS x 8 BIT CMOS STATIC RAM D escription The GM76C88L is 65,536 bit static random access memory organized as 8,192 words by 8 bits us­ ing CMOS technology and operated from a sin­

Contextual Info: Wm High-Performance 128 KByte Asynchronous Cache Module AS7M32DI28 PRELIMINARY 128 KHyte Asynchronous Cache Module | FEATURES _ _ _ I PIN ARRANGEMENT • 128 KByte secondary cache module - Data: 32,768 wards x 32 bits - Tag: 8,192 words x 8 bits - Dirty: 8,192 words x 1 bit

Contextual Info: DS1643/DS1643P-70/100 PRELIMINARY DALLAS SEMICONDUCTOR DS1643/DS1643P-70/100 Nonvolatile Timekeeping RAM FEATURES PIN ASSIGNMENT • Integrated NV SRAM, real time clock, crystal, powerfail control circuit and lithium energy source NC 0 1 28 B A12 0 2 270 WE

KMM5368100-6

Abstract: KMM5368100-8 KMM5368100-7
Contextual Info: SAMSUNG ELECTRONICS INC b7E D WÊ 7 T b m 4 S KMM5368100/G OOISETÖ ÖDE BiSflSK DRAM MODULES 8M x36 DRAM SIMM Memory Module FEATURES GENERAL DESCRIPTION • Performance range: KMM5368100-6 • • • • • • • tfiAC tCAC tRC 60ns 15ns 110ns KMM5368100-7

HM6287-70

Contextual Info: H M 6 2 8 7 S e r ie s Maintenance Only 65536-word x 1-bit High Speed CMOS Static RAM Refer to HM6287H Series • FEATURES • High Speed: Fast Access Time 45/55/70ns max. • • Single 5V Supply and High Density 22 Pin Package Low Power Standby and Low Power Operation

Contextual Info: CY29FCT818T 5f CYPRESS Diagnostic Scan Register Features Functional D escription • Function, pinout and drive compatible with FCT, F Logic and AM29818 • FCT-C speed at 6.0 ns max. Com'l FCT-B speed at 7.5 ns max. (Com’l) • Reduced Vqh (typically = 3JV)

M83C

Abstract: 0PB2 83C55
Contextual Info: O K I semiconductor MSM83C55-XXRS/GS/JS 2048 x 8 BIT MASK ROM WITH I/O PORTS GENERAL DESCRIPTION The M SM 83C 55 is a com bination o f MROM and I/O devices used in a microcom puter system. Owing to the adop­ tion o f the CMOS silicon gate technology, it operates on a power supply as small as 100 pA max. standby cur­

Contextual Info: 16K x 4 Static RAM FEATURES □ 16K x 4 Static RAM with Separate I/O , Transparent Write L7C161 , or High Impedance Write (L7C162) □ Auto-Powerdown Design □ Advanced CMOS Technology □ H ighspeed — to 8 ns maximum □ Low Power Operation Active: 210 mW typical at 35 ns

Mem 5116

Abstract: D100D 9F59 1F50 pace1750 PIC dmx example codes P4C168 P4C187 PACE1750A PACE1754
Contextual Info: PERFORMANCE SEMI CONDUCTOR 20E D 70^25=17 PACE1751/1753 SINGLE CHIP, 40 MHz CMOS MMU/COMBO GQ00i7b b • C ^ ilL Q M iM M Y T - 5*3. FEATURES ■ Implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megawords. All mapping

TAG 503

Abstract: AL TECH CD06 CD-03
Contextual Info: 8I 1l High-Performance 256 KB We Asynchronous Cache Module AS7M32W256 PRELIM INARY 256 KByte Asynchronous Cache Module |FEATURES I PIN ARRANGEMENT • 256 KByte secondary cache module 64 pin dual-readout SIMM - Bank A: 32,768 wards x 32 bits - Same pinout for 128/256KB

HM511002-12

Abstract: ir 2210 ic
Contextual Info: Preliminary HM511002S Series 1048576-word x 1-bit CMOS Dynamic Random Access Memory T h e H ita c h i H M 5 1 1 0 0 2 S Series is a C M O S d y n a m ic R A M HM511002SP Series org anized 1 0 4 8 5 7 6 -w o rd x 1-bit. H M 5 1 1 0 0 2 S has rea lized higher

Contextual Info: P r o d u c t S p e c if ic a t io n Z8440/1/2/4, Z84C40/1/2/3/4 S e r ia l in p u t / o u t p u t Co n t r o l le r FEATURES • Two independent full-duplex channels, with separate control and status lines for m odem s or other devices. ■ Data rate in the x1 dock mode of 0 to 2.0M bits/