LH5332P00 Search Results

LH5332P00N

Abstract: 44-PIN 48-PIN
Contextual Info: CMOS 32M 4M x 8/2M × 16 Mask-Programmable ROM LH5332P00 FEATURES • 4,194,304 words × 8 bit organization (Byte mode) 2,097,152 words × 16 bit organization (Word mode) • Access time: 120 ns (MAX.) • Power consumption: Operating: 440 mW (MAX.) Standby: 550 µW (MAX.)

Contextual Info: LH5332P00 FEATURES • 4,194,304 words x 8 bit organization Byte mode 2,097,152 words x 16 bit organization (Word mode) • Access time: 120 ns (MAX.) • Power consumption: Operating: 440 mW (MAX.) Standby: 550 ^.W (MAX.) • Static operation • TTL compatible I/O

Contextual Info: LH5332P00 FEATURES • 4,194,304 words x 8 bit organization Byte mode 2,097,152 words × 16 bit organization (Word mode) • Access time: 120 ns (MAX.) • Power consumption: Operating: 440 mW (MAX.) Standby: 550 µW (MAX.) • Static operation • TTL compatible I/O

LHMN5

Abstract: 48TSOP LH5332600 LH5332600N LH5332600T LH5332C00D TSOP048-P-1218 LH5332500 2sj au LHMV
Contextual Info: NBA/ INFORMATION LH5332600 • High-speed 32M-bit Mask-Programmable ROM Pin Connections Description The LH5332600N/T User's No. : LHMN56XX/LHMN5FXX is a CM OS 32M-bit mask-programmable ROM organized as 4 194 304X8 bits (Byte mode) or 2 097 152X 16 bits (Word

MB8316200

Abstract: uPD23C4000S TC533200 23C4000C UPD23C4000 23C32000a 624116 HN62318/338B
Contextual Info: MEMORY ICS FUNCTION GUIDE 3. CROSS REFERENCE GUIDE Density 4M bit 8M bit Samsung NEC Hitachi Sharp Toshiba Fujitsu K M 23C4000C UPD23C4001EB HN62344B LH534700 TC534000C M B834000A K M 23C4100C UPD23C4000S HN62444 LH534600B TC534200C M B834200A K M 23C 4; OOCET UPD23C4000S

536G

Abstract: LH534600
Contextual Info: MEMORIES • Mask ROMs Process Capacity * Configuration words X bits Pinout Access time Model No. (ns) MIN. Supply current (mA) MAX. Supply voltage (V) (ns) MAX. User's No. Cycle tima Package 256k 32k X 8 J LH53259D/N/T L H 5359X X 150 25 5 ± 10% 28DIP/28SOP/28TSOP(I)

lh5s4

Abstract: lh537 48-TSOP LH5s 42-DIP 48TSOP1 LH5364P00D LH538 LH5S46
Contextual Info: MEMORIES • Mask ROM Specific Pinout ★ U n d e rd e v e lo p m e n t • 3 V 3 .3 V operation Access time B it C a p a c ity configuration 1M x8 2M x 8/x 16 4M x 8/x 16 8M x 8/x 16 16M x 8/x 16 32 M x 8/x 16 64M 128M * x 8/x 16 x 16 Readable at 2.7 V.

lh537

Abstract: 42DIP lh533200 LH535g
Contextual Info: MEMORIES • Mask ROMs Process CMOS ★ U n d e r development MEMORIES ★ Under developm ent Configuration Process Capacity (wortsxbits Access time (ns) MAX. Model No. Pinout LH-538VXX 100 100 5 ± 10% 32DIP/32SOP/32TSOPÎII) Normal 120 60 5 ± 10% L H 5 3 8 3 0 0 C D /C W C S Æ S H

flash 64m

Contextual Info: MEMORIES Mask ROMs C a p a c ity Access time C o nfig u ra tio n 120ns 100ns 80ns 150ns 256kj I 32k x 8 ] LH53259 12k I 64k x 8 LH53517 128k x 8 LH530800A LH531V00 1M LH531024 64k x 16 i LH532100B-1 256k x 8 ! LH532100B 2M JEDEC standard EPROM pinout 128k x 161

Contextual Info: CMOS 32M 4 M x 8/ 2M x 16 MROM FEATURES 4 4 -P IN S O P ^ a 19 A 17|Z 42 D a 7 C 4 41 HI A g a 6 d 5 40 ^ 5 C 6 39 Zl A ^ A 4 IZ 7 38 Zl a 12 A 3 d 8 37 Zl a 13 A2 d 9 36 Zl a 14 A id 10 35 Zl a 15 16 a Standby: 550 (iW (MAX.) • Static operation DESCRIPTION

LQ070T5BG01

Abstract: LM24P20 LM162KS1 BSCR86L00 IR2C07 LM5Q31 IR3Y29B BSCU86L60 lq6bw lq6bw506
Contextual Info: INDEX 1 0 4 - 1 0 9 _ DC_ GL1PR112.69 GL3KG63. 66 GL5EG41.66 1 0 4 - n 0 5 O o c .113 DC1B1CP. 100 GL1PR135.69 GL3KG8. 66

Contextual Info: MEMORIES ★ Capacity Configuration * 1 C om patible with 4 M -bit flash m em ories from A d vanced M icro D evices, Inc. * 2 C om patible with 4 M -bit flash m em ories from Intel Corp. A c c e s s tim e Under development MEMORIES ★ Under development Access time

IR3Y29B

Abstract: ir3y26a1 IR4N IR3T24N IR3C08N ir2c53 ir2c05 li3301 IR3Y08 IR2E02
Contextual Info: Index Model No. IR3T ARM710 ARM7DI ARM7DM ARM7TDMI ARM7TDMI-SPL ARM8 ARM810 CMOS CMOS CMOS CMOS F series G series J series K series ID22 series ID222XX ID223XX ID224XX ID226XX ID227XX ID229XX ID22DXX ID22FXX ID22HXX ID240 series ID240DXX ID240EXX ID240GXX

Contextual Info: CMOS 3 2 M 4 M x 8/2 M x 16 MROM FEATURES • 4,194,304 words x 8 bit organization (Byte mode) 2,097,152 words x 16 bit organization (Word mode) • Access time: 120 ns (MAX.) • Power consumption: Operating: 440 mW (MAX.) Standby: 550 \i\N (MAX.) • Static operation

IR2E27A

Abstract: IR2C53 IR2E02 IR2E27 IR2E10 IR3N34 IR2E31A IR2E01 IR2C07 ir2e31
Contextual Info: lndeX Model No. ARM7D CPU Core28,32,33 ARM7DM 28,33 CMOS CMOS CMOS CMOS 76 5A A F G 44 44 44 44 ID1 series ID2 series ID3 seríes ID21K064 ID21K128 ID21K256 ID21K512 ID21M010 ID21M015 ID21M020 ID21M040 ID22K256 ID22K512 ID22M010 ID22M020 ID22M040 ID22M080

LHMN5

Abstract: sharp mask rom 44-pin LH5332600N 2MX16 LH5332600 LH5332600T LH5332C00D LH535
Contextual Info: LH5332600 • Description High-speed 32M-bit Mask-Programmable ROM Pin Connections . The LH5332600N/T User’s No. : LHMN56XX/LHMN5FXX is a CMOS 32M-bit mask-programmable ROM organized as 4 194 3 0 4 X 8 bits (Byte mode) or 2 097 152 X 16 bits (Word mode) that can be selected by BYTE input pin.

TB 1275 an

Contextual Info: CMOS 32M 4M x 8/2M x 16 Mask-Programmable ROM L H 5 3 3 2 P00 FEATURES PIN CONNECTIONS • 4,194,304 words x 8 bit organization 44-PIN SOP TOP VIEW r (Byte mode) 2,097,152 words x 16 bit organization (Word mode) • Access time: 120 ns (MAX.) • Power consumption: