DN74LS3 Search Results

DN74LS395A

Abstract: MA161
Contextual Info: DN74LS395A LS TTL DN74LS Series DN74LS395A 4 -b it Cascadable Shift R egisters with 3 -sta te Outputs • D escription P -2 D N 74LS395A is a 4-bit serial/parallel input to serial/parallel o u tp u t shift register w ith 3-state outputs. ■ Features •

DN74LS366A

Abstract: MA161
Contextual Info: DN74LS366A LS TTL DN74LS Series DN74LS366A 74 LSSfeCPr Hex B u s D riv e r s with 3 - s t a * e Outputs • Description D N 74LS366A P -2 c o n t a in s s ix 3 -state o u tp u t^ in v e rte r b u ffe r c ir c u it s w ith c o m m o n o u tp u t - c o n t r o l in p u ts G i a n d G 2 .

741s

Abstract: CI 741S DN74LS30 MA161
Contextual Info: LS TTLDN74LS Series DN74LS30 DN74LS30 £>to 7a LS 30 8 - input P o sitiv e N AN D Gates B Description P-1 DN 74LS30 contains one 8-input positive isolation NAND gate circuit. • Features • • • • Low pow er consum ption Pd = 2.5m W typical High speed ( t pd = 1 In s typical)

5v constant power supply lob

Abstract: D107 DN74LS32
Contextual Info: LS TTL DN74LS Series DN74LS32 D N 74L S 32 î 3^ Quad 2 - input Positive OR Gates • D escription DN74LS32 contains four 2-input positive isolation OR gate circuits. P-1 H Features • • • • Low power consumption Pd = 20mW typical) High speed (tpd = 14ns typical)

Contextual Info: LS TTL DN74LS Series DN74LS373 DN74LS373 Octal D-type Transparent L a t c h e s w ith 3 -sta te Outputs • Description P-3 D N74LS373 contains eight 3-state o u tp u t D-type latch circuits w ith com m on outp u t-control enable inputs for all circuits.

Contextual Info: LS TTL DN74LS Series DN74LS365A DN74LS365A 141S&S3Y Hex Bus Drivers with 3-state Outputs • Description DN74LS365A contains six 3-state output buffer circuits with common output-control inputs Gi and G2 . P-2 ■ Features • High fan-out (I ol = 24mA, Ioh = —2.6mA)

Contextual Info: LS TTL DN74LS Series DN74LS395A DN74LS395A 4 - bit Cascadable Shift Registers with 3 -sta te Outputs • Description P -2 D N 7 4 L S3 9 5 A is a 4-b it serial/parallel input to serial/parallel output shift register w ith 3-state outputs. ■ Features • Synchronous serial/parallel input to serial/parallel output

Contextual Info: LS TTL DN74LS Series DN74LS33 DN74LS33 Dfo74<-S33 Quad 2 - input Positive NOR Buffers with Open Collector Outputs • Description P-1 DN74LS33 contains four 2-input positive isolation NOR buffer gates w ith open collector outputs. H Features • “W ired” AND capability

Contextual Info: LS TTL DN74LS Series DN74LS386 DN74LS386 N>74LS3?£ Quad 2 -input E xclu sive OR G ates • Description P-1 D N 74LS386 contains four 2-input exclusive O R gate circuits. ■ Features • • • • Low pow er consum ption Pd = 30.5m W typical High speed ( tpd = 1 In s typical)

Contextual Info: DN74LS366A LS TTL DN74LS Series DN74LS366A Hex Bus D rivers with 3-sta*e Outputs • Description P-2 D N 74LS366A contains six 3-state output_ inverter buffer circuits w ith com m on output-control inputs G i and G2 . ■ Features • • • Com m on o u tp u t-control inputs for all six circuits

Contextual Info: PAN ASONIC IND L/ELEK -CIC3- 75 Ï F | bTBEñSa D007SSM 3 6 932 852 PANASONIC IND L *ELECTRONIC 72C 0 7 2 5 4 LS TTL DN74LS^U-X D DN74LS377/DN74LS377S DN74LS377/DN74LS377S Octal Positive Edge-Triggered D-Type Flip-Flops with Enable D N 7 4 L S 3 7 7 /S IÍ, è - » * ® « 7 0 7 ? *>' J c íM

Contextual Info: I LS TTL DN74LS Series DN74LS368A DN74LS368A Hex Bus Drivers with 3-state Outputs • Description P-2 DN 74LS368A contains six 3-state o u tp u t inverter buffer circuits w ith outp u t-control inputs G! and G2 for four and two circuits respectively. ■ Features

DN74LS38

Contextual Info: I LS TTL DN74LS Series DN74LS38 DN74LS38 Quad 2 - input P o sitiv e NAND B uffers w ith Open C ollector Outputs • Description P-1 DN74LS38 contains four 2-input positive isolation NAND buffer gate circuits with open collector outputs. H Features • •

Contextual Info: PANASONIC INDL/ELEK {IC> 72 6 9 3 2 8 6 2 L S T T L P A N A S O N IC D e J ^ 3 2 0 5 2 0D0724Ö fl [j*' IN D t:;E L E C T R O N l £ ^ ^ ^ ;7 ^ C ^ 7 2 4 8 y D N 7 4 L S i^ U — X O ^ ^ , D N 74LS3 7 4 /D N 7 4 LS3 7 4 S T - 4 I0 - 0 7 - 0 S DN74LS374/DN74LS374S

Contextual Info: L S T T L DN74LS Series DN74LS32 T DN74LS32 107 ^ L - S 3 ^ Quad 2 - input P ositive OR Gates • Description P-1 DN74LS32 contains four 2-input positive isolation OR gate circuits. ■ Features • • • • Low pow er consum ption P d = 20mW typical)

74LS378

Contextual Info: P A N A S O N I C I N D L / E L E K 6 9 3 2 8 5,2 P ANASO NIC 7 5 - C I O D b T 3 5 â S S e | I N D U ELECTRON IC 72C LS TTL DN74LSf>U-X □ D 0 7 E S L 0 72 56 7 _ D DN74LS378/DN74LS378S T - M U - CT7- O S DN74LS378 DN74LS378S Hex P o sitiv e E d ge-T riggered D -T ype Flip-Flops with Enable

DN74LS37

Abstract: MA161 at3y
Contextual Info: DN74LS37 LS T T L DN74LS Series DN74LS37 Quad 2 - input Positive NAND Buffers • Description DN74LS37 contains four 2-input positive isolation NAND buffer gate circuits. ■ Features • • • • • High fan-out I o l = 24mA, I o h = —1.2mA Low power consumption (P<j = 17.5mW typical)

S020D

Abstract: s5b0
Contextual Info: PANASONIC IN D L /E L E K - C I O 7 5 _ , 6 ?^3J § H ,± A .N A S o n IC • ' D ? | t l B B f l S S G0 0 7 5 S 4 3 ^ -* - ' . . - • - ' 72C 0 7 2 54 in d u elec t r o n ic LS TTL DN74LS^U-X D DN74LS377/DN74LS377S T H É -tn -fc Ç DN74LS377/DN74LS377S

DN74LS373

Contextual Info: LS TTL DN74LS Series DN 74LS373 DN74LS373 K>74 LS. 373 Octal D-type Transparent Latches with 3 -sta te Outputs • Description D N 74L S 373 con tain s eight 3-state o u tp u t D -type latch circuits w ith com m on o u tp u t-c o n tro l enable in puts for all circuits.

DN74LS33

Contextual Info: I DN74LS33 LS TTL DN74LS Series DN74LS33 Quad 2 - input P o sitiv e NOR B uffers with Open C ollector Outputs P-1 • D escription DN 74LS33 contains four 2-input positive isolation NOR buffer gates w ith open collector outputs. ■ Features • • •

pht 094

Abstract: 400M DN74LS196 MA161
Contextual Info: LS TTL DN74LS Series D N 7 4 L S 1 9 DN74LS3 96 6 30M H z S ettable Decade Counters / L atches I D e s c rip tio n D N 74LS196 is an asynchronous decade counter with directcoupled reset input and set input. P-1 • Features • Direct-coupled reset input and asynchronous set input

Contextual Info: LS TTL DN74LS Series DN74LS30 DN741S30 £1074 IS 3 0 8 - input Positive NAND Gates H Description P-1 DN 74LS30 contains one 8-input positive isolation NAND gate circuit. • Features • • • • Low pow er consum ption P^ = 2.5mW typical High speed ( t pd = 1 In s typical)

Contextual Info: LSTTL DN74LS Series DN74LS32 DN74LS32 Quad 2 - input Positive OR Gates • Description P-1 DN74LS32 contains four 2-input positive isolation OR gate circuits. ■ Features • Low power consumption P< = 20mW typical) • High speed (tp<i = 14ns typical)

Contextual Info: LS TTL DN74LS Series DN74LS366A DN74LS366A 74 L Hex Bus Drivers with 3-sta*e Outputs • Description DN74LS366A contains six 3-state output inverter buffer circuits with common output-control inputs Gi and G2 . P-2 ■ Features • Common output-control inputs for all six circuits