DDR400A Search Results

Contextual Info: PRELIMINARY V58C2256 804/404/164 S HIGH PERFORMANCE 256 Mbit DDR SDRAM 4 BANKS X 8Mbit X 8 (804) 4 BANKS X 4Mbit X 16 (164) 4 BANKS X 16Mbit X 4 (404) MOSEL VITELIC 5 6 7 75 8 DDR400A DDR333B DDR266A DDR266B DDR200 7.5 ns 7.5 ns 7.5ns 10 ns 10 ns Clock Cycle Time (tCK2.5)

128MB PC3200 DDR CL3

Contextual Info: NT128D64SH4B1G-5 128MB : 16M x 64 PC3200A Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM Based on DDR400A 16Mx16 SDRAM Features • 16Mx64 Unbuffered DDR DIMM based on 16Mx16 DDR • DRAM DLL aligns DQ and DQS transitions with clock transitions SDRAM • Address and control signals are fully synchronous to positive

Contextual Info: NT128D64SH4B1G-5 128MB : 16M x 64 PC3200A Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM Based on DDR400A 16Mx16 SDRAM Features • 16Mx64 Unbuffered DDR DIMM based on 16Mx16 DDR • DRAM DLL aligns DQ and DQS transitions with clock transitions SDRAM • Address and control signals are fully synchronous to positive

09 0134 70 02

Contextual Info: NT256D64S88B1G-5 256MB : 32M x 64 PC3200A Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM Based on DDR400A 32Mx8 SDRAM Features • 32Mx64 Unbuffered DDR DIMM based on 32Mx8 DDR SDRAM • DRAM DLL aligns DQ and DQS transitions with clock transitions • JEDEC Standard 184-pin Dual In-Line Memory Module

A 14U

Abstract: DDR200 DDR266A DDR266B DDR333B DDR400 DDR400A PC2100 PC2700 PC3200
Contextual Info: PRELIMINARY V58C2256 804/404/164 S HIGH PERFORMANCE 256 Mbit DDR SDRAM 4 BANKS X 8Mbit X 8 (804) 4 BANKS X 4Mbit X 16 (164) 4 BANKS X 16Mbit X 4 (404) MOSEL VITELIC 5B 5 6 7 75 8 DDR400A DDR400A DDR333B DDR266A DDR266B DDR200 7.5 ns 7.5 ns 7.5 ns 7.5ns 10 ns

nanya nt5ds32m8bt-5t

Abstract: DDR400A DDR400B NT5DS16M16BT NT5DS32M8BT NT5DS64M4BT
Contextual Info: NT5DS64M4BT NT5DS64M4BF NT5DS32M8BT NT5DS32M8BF NT5DS16M16BT NT5DS16M16BF 256Mb DDR SDRAM Features • • • • • CAS Latency and Frequency CAS Latency 3 2.5 Maximum Operating Frequency MHz DDR400A DDR400B (-5) (-5T) 200 200 200 166 • • • •

CY28352

Abstract: CY28352OC CY28352OCT CY28352OXC
Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.

TSOP-66

Abstract: DDR400 DDR400A DDR400B HYB25D256 HYB25D256800BT TSOP66 266DR
Contextual Info: HYB25D256[800/160]BT L -[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Jan. 2003, V0.9 Features CAS Latency and Clock Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400B DDR400A -5 -5A 133 133 166 200 200 200

NT5DS32M8BT-5T

Abstract: DDR400A DDR400B NT5DS16M16BT NT5DS32M8BT NT5DS64M4BT
Contextual Info: NT5DS64M4BT NT5DS64M4BF NT5DS32M8BT NT5DS32M8BF NT5DS16M16BT NT5DS16M16BF 256Mb DDR SDRAM Features • • • • • CAS Latency and Frequency CAS Latency 3 2.5 Maximum Operating Frequency MHz DDR400A DDR400B (-5) (-5T) 200 200 200 166 • • • •

Contextual Info: NT5DS64M4BT NT5DS64M4BF NT5DS32M8BT NT5DS32M8BF NT5DS16M16BT NT5DS16M16BF 256Mb DDR SDRAM Features • • • • • CAS Latency and Frequency CAS Latency 3 2.5 Maximum Operating Frequency MHz DDR400A DDR400B (-5) (-5T) 200 200 200 166 • • • •

Contextual Info: NT128D64SH4B1G-5 128MB : 16M x 64 PC3200A Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM Based on DDR400A 16Mx16 SDRAM Features • 16Mx64 Unbuffered DDR DIMM based on 16Mx16 DDR • DRAM DLL aligns DQ and DQS transitions with clock transitions SDRAM • Address and control signals are fully synchronous to positive

TCk100

Contextual Info: PRELIMINARY V58C2256 804/404/164 S HIGH PERFORMANCE 256 Mbit DDR SDRAM 4 BANKS X 8Mbit X 8 (804) 4 BANKS X 4Mbit X 16 (164) 4 BANKS X 16Mbit X 4 (404) MOSEL VITELIC 5 6 7 75 8 DDR400A DDR333B DDR266A DDR266B DDR200 7.5 ns 7.5 ns 7.5ns 10 ns 10 ns Clock Cycle Time (tCK2.5)

Contextual Info: NT512D64S8HB1G-5 512MB : 64M x 64 PC3200A Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM Based on DDR400A 32Mx8 SDRAM Features • 64Mx64 Unbuffered DDR DIMM based on 32Mx8 DDR SDRAM • DRAM DLL aligns DQ and DQS transitions with clock transitions • JEDEC Standard 184-pin Dual In-Line Memory Module

Contextual Info: NT512D64S8HB1G-5 512MB : 64M x 64 PC3200A Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM Based on DDR400A 32Mx8 SDRAM Features • 64Mx64 Unbuffered DDR DIMM based on 32Mx8 DDR SDRAM • DRAM DLL aligns DQ and DQS transitions with clock transitions • JEDEC Standard 184-pin Dual In-Line Memory Module

Contextual Info: NT5DS64M4BT NT5DS64M4BF NT5DS32M8BT NT5DS32M8BF NT5DS16M16BT NT5DS16M16BF 256Mb DDR SDRAM Features • • • • • CAS Latency and Frequency CAS Latency 3 2.5 Maximum Operating Frequency MHz DDR400A DDR400B (-5) (-5T) 200 200 200 166 • • • •

CY28352

Abstract: CY28352OC CY28352OCT CY28352OXC
Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.

16MX16

Contextual Info: V58C2256 804/404/164 SA HIGH PERFORMANCE 256 Mbit DDR SDRAM 4 BANKS X 8Mbit X 8 (804) 4 BANKS X 4Mbit X 16 (164) 4 BANKS X 16Mbit X 4 (404) 5B 5 6 7 DDR400A DDR400A DDR333B DDR266A 7.5 ns 7.5 ns 7.5 ns 7.5ns Clock Cycle Time (tCK2.5) 5ns 6ns 6 ns 7ns Clock Cycle Time (tCK3)

Contextual Info: NT256D64S88B1G-5 256MB : 32M x 64 PC3200A Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM Based on DDR400A 32Mx8 SDRAM Features • 32Mx64 Unbuffered DDR DIMM based on 32Mx8 DDR SDRAM • DRAM DLL aligns DQ and DQS transitions with clock transitions • JEDEC Standard 184-pin Dual In-Line Memory Module

Contextual Info: NT5DS64M4BT NT5DS64M4BF NT5DS32M8BT NT5DS32M8BF NT5DS16M16BT NT5DS16M16BF 256Mb DDR SDRAM Features • • • • • CAS Latency and Frequency CAS Latency 3 2.5 2 Maximum Operating Frequency MHz DDR400A/B/C (-5) 200 200 133 • • • • • • •

Contextual Info: NT5DS64M4BT NT5DS64M4BF NT5DS32M8BT NT5DS32M8BF NT5DS16M16BT NT5DS16M16BF 256Mb DDR SDRAM Features • • • • • CAS Latency and Frequency CAS Latency 3 2.5 2 Maximum Operating Frequency MHz DDR400A/B/C (-5) 200 200 133 • • • • • • •

Contextual Info: NT512D64S8HB1G-5 512MB : 64M x 64 PC3200A Unbuffered DDR DIMM 184pin Unbuffered DDR DIMM Based on DDR400A 32Mx8 SDRAM Features • 64Mx64 Unbuffered DDR DIMM based on 32Mx8 DDR SDRAM • DRAM DLL aligns DQ and DQS transitions with clock transitions • JEDEC Standard 184-pin Dual In-Line Memory Module

Contextual Info: V58C2128 804/404/164 SB HIGH PERFORMANCE 128 Mbit DDR SDRAM 4 BANKS X 4Mbit X 8 (804) 4 BANKS X 2Mbit X 16 (164) 4 BANKS X 8Mbit X 4 (404) 5B 5 6 7 DDR400A DDR400A DDR333B DDR266A 7.5 ns 7.5 ns 7.5 ns 7.5ns Clock Cycle Time (tCK2.5) 5ns 6ns 6 ns 7ns Clock Cycle Time (tCK3)

Contextual Info: V58C2256 804/404/164 SB HIGH PERFORMANCE 256 Mbit DDR SDRAM 4 BANKS X 8Mbit X 8 (804) 4 BANKS X 4Mbit X 16 (164) 4 BANKS X 16Mbit X 4 (404) 5B 5 6 7 DDR400A DDR400A DDR333B DDR266A 7.5 ns 7.5 ns 7.5 ns 7.5ns Clock Cycle Time (tCK2.5) 5ns 6ns 6 ns 7ns Clock Cycle Time (tCK3)

Contextual Info: V826616J24SC 16M x 64 HIGH PERFORMANCE UNBUFFERED DDR SDRAM MODULE Features Description • 184 Pin Unbuffered 16,777,216 x 64 bit Organization DDR SDRAM Modules ■ Utilizes High Performance 16M x 16 DDR SDRAM in TSOPII-66 Packages ■ Single +2.5V ± 0.2V Power Supply