CY28352OXC Search Results

CY28352OXC Datasheets (2)

Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
CY28352OXC		Cypress Semiconductor	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant	Original	PDF	115.76KB	8
CY28352OXC		Spectra Linear	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant	Original	PDF	117.06KB	7

CY28352OXC Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
CY28352 Abstract: CY28352OC CY28352OCT CY28352OXC Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.	Original	CY28352 DDR400and DDR333-Compliant 333-MHz 400-MHz 200-MHz CY28352 DDR400- DDR333-Compliant, CY28352OC CY28352OCT CY28352OXC	PDF
CY28352 Abstract: CY28352OC CY28352OCT CY28352OXC Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.	Original	CY28352 DDR400and DDR333-Compliant 333-MHz 400-MHz 200-MHz CY28352 DDR400- DDR333-Compliant, CY28352OC CY28352OCT CY28352OXC	PDF
CY28352 Abstract: CY28352OC CY28352OCT CY28352OXC Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features Description • Supports 333 MHz and 400-MHz DDR SDRAM • 60- 200 MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.	Original	CY28352 DDR400- DDR333-Compliant 400-MHz CY28352 CY28352OC CY28352OCT CY28352OXC	PDF

Catalog Datasheet

Type

Document Tags

PDF

CY28352

Abstract: CY28352OC CY28352OCT CY28352OXC
Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.

Original

CY28352 DDR400and DDR333-Compliant 333-MHz 400-MHz 200-MHz CY28352 DDR400- DDR333-Compliant, CY28352OC CY28352OCT CY28352OXC

PDF

CY28352

Original

CY28352 DDR400and DDR333-Compliant 333-MHz 400-MHz 200-MHz CY28352 DDR400- DDR333-Compliant, CY28352OC CY28352OCT CY28352OXC

PDF

CY28352

Abstract: CY28352OC CY28352OCT CY28352OXC
Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features Description • Supports 333 MHz and 400-MHz DDR SDRAM • 60- 200 MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.

Original

CY28352 DDR400- DDR333-Compliant 400-MHz CY28352 CY28352OC CY28352OCT CY28352OXC

PDF