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CY28352OXC Datasheets (2)

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Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
CY28352OXC		Cypress Semiconductor	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant	Original	PDF	115.76KB	8
CY28352OXC		Spectra Linear	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant	Original	PDF	117.06KB	7

CY28352OXC Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
CY28352 Abstract: CY28352OC CY28352OCT CY28352OXC Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.	Original	cy28352 ddr400and ddr333-compliant 333-mhz +6400-mhz 200-mhz ddr400-cy28352oc cy28352oct cy28352oxc	PDF
CY28352 Abstract: CY28352OC CY28352OCT CY28352OXC Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.	Original	cy28352 ddr400and ddr333-compliant 333-mhz +6400-mhz 200-mhz ddr400-cy28352oc cy28352oct cy28352oxc	PDF
CY28352 Abstract: CY28352OC CY28352OCT CY28352OXC Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features Description • Supports 333 MHz and 400-MHz DDR SDRAM • 60- 200 MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.	Original	cy28352 ddr400-ddr333-compliant 400-mhz +3cy28352oc cy28352oct cy28352oxc	PDF

Catalog Datasheet

Type

Document Tags

PDF

CY28352

Abstract: CY28352OC CY28352OCT CY28352OXC
Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.

Original

cy28352 ddr400and ddr333-compliant 333-mhz +6

PDF

CY28352

Original

cy28352 ddr400and ddr333-compliant 333-mhz +6

PDF

CY28352

Abstract: CY28352OC CY28352OCT CY28352OXC
Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features Description • Supports 333 MHz and 400-MHz DDR SDRAM • 60- 200 MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.

Original

cy28352 ddr400-ddr333-compliant 400-mhz +3

PDF