CY28352OC Search Results

CY28352OC Datasheets (5)

Filter by Manufacturer

Select Manufacturer

Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
CY28352OC		Cypress Semiconductor	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant	Original	PDF	115.76KB	8
CY28352OC		Cypress Semiconductor	Differential Clock Buffer/Driver	Original	PDF	85.23KB	9
CY28352OCT		Cypress Semiconductor	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant	Original	PDF	115.76KB	8
CY28352OCT		Cypress Semiconductor	Differential Clock Buffer/Driver	Original	PDF	85.23KB	9
CY28352OCT		Spectra Linear	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant	Original	PDF	117.06KB	7

CY28352OC Price and Stock

Filter by Manufacturer

Cypress Semiconductor


Cypress Semiconductor CY28352OC DDR ZDB Buffer for SiS Chipset
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Rochester Electronics	CY28352OC		91		1	1 - 10 - 100 $2.38 1000 $2.13 10000 $2.00	Buy Now

CY28352OC Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: CY28352 Differential Clock Buffer/Driver Features Description • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to six differential outputs • External feedback pin FBIN is used to synchronize	Original	cy28352 28-pin	PDF
CY28352 Abstract: CY28352OC CY28352OCT CY28352OXC Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.	Original	cy28352 ddr400and ddr333-compliant 333-mhz +6400-mhz 200-mhz ddr400-cy28352oc cy28352oct cy28352oxc	PDF
CY28352OC Abstract: DDR400 Contextual Info: CY28352-400 Differential Clock Buffer/Driver DDR400 and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60–273-MHz operating frequency This PLL clock buffer is designed for 2.6VDD and 2.6AVDD operation and differential output levels.	Original	cy28352-400 ddr400 ddr333-compliant 333-mhz +3400-mhz 273-mhz cy28352oc	PDF
CY28352 Abstract: CY28352OC CY28352OCT CY28352OXC Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.	Original	cy28352 ddr400and ddr333-compliant 333-mhz +6400-mhz 200-mhz ddr400-cy28352oc cy28352oct cy28352oxc	PDF
47AB Abstract: SCD1U16V3KX BCB25 BC536 BC163 216t9 sis645dx foxconn WISTRON BC466 Contextual Info: CLK GEN TOUCAN2 DesKtop-CPU Northwood 2.2~3.06GHz ICS:ICS952004AG DDRBUF:ICS93732 3,4 5,6 VRAM2 FSB 533/400MHz K4D263238M-QC40 CRT 17 2.5V 200MHz/266MHz DDR 2 11,12,13 SiS962 24 CD-ROM AGP 4X W/RTC 15" MII LAN MAC PHY 20,21,22,23 1394 conn. Agere FW802A	Original	ics952004ag ics93732 06ghz k4d263238m-qc40 +15533/400mhz 200mhz/266mhz 47y01 sis645dx 66mhz 16bits/533mbs 47ab scd1u16v3kx bcb25 bc536 bc163 216t9 foxconn wistron bc466	PDF
1g22SB Abstract: SB3211 BC741 SIS 648 SB315 CP2216 AMS1117 1104 BC246 RB342 diode sb315 Contextual Info: M A R G A I D K C O L B M E T S Y S D 3 K PCB LAYER High Speed DDR-SDRAM K4D263238A-GC36 Clock Gen CY28381 100MHz P.17,18 DeskTop CPU Northwood FSB 400/533MHz P.11 2.5V 266/333MHz P.19 275MHz P.5,6 P.3 DDR*2 CRT CONN Delay Buffer CY28352 2.5V 266/333MHz P.4	Original	cy28381 k4d263238a-gc36 100mhz 400/533mhz +15275mhz 266/333mhz cy28352 nv18-pro 133mhz 1g22sb sb3211 bc741 sis 648 sb315 cp2216 ams1117 1104 bc246 rb342 diode sb315	PDF
CY28352 Abstract: CY28352OC CY28352OCT CY28352OXC Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features Description • Supports 333 MHz and 400-MHz DDR SDRAM • 60- 200 MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.	Original	cy28352 ddr400-ddr333-compliant 400-mhz +3cy28352oc cy28352oct cy28352oxc	PDF
CY28352 Abstract: CY28352OC CY28352OCT Contextual Info: CY28352 Differential Clock Buffer/Driver Features Description • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to six differential outputs • External feedback pin FBIN is used to synchronize	Original	cy28352 28-pin cy28352oc cy28352oct	PDF
CY28352 Abstract: CY28352OC CY28352OCT DDR333 DDR400 Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400- and DDR333 Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications	Original	cy28352 ddr400-ddr333 333-mhz +6400-mhz 200-mhz 28-pin cy28352oc cy28352oct ddr400	PDF