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CY28352OCT Datasheets (3)

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Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
CY28352OCT		Cypress Semiconductor	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant	Original	PDF	115.76KB	8
CY28352OCT		Cypress Semiconductor	Differential Clock Buffer/Driver	Original	PDF	85.23KB	9
CY28352OCT		Spectra Linear	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant	Original	PDF	117.06KB	7

CY28352OCT Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: CY28352 Differential Clock Buffer/Driver Features Description • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to six differential outputs • External feedback pin FBIN is used to synchronize	Original	cy28352 28-pin	PDF
CY28352 Abstract: CY28352OC CY28352OCT CY28352OXC Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.	Original	cy28352 ddr400and ddr333-compliant 333-mhz +6400-mhz 200-mhz ddr400-cy28352oc cy28352oct cy28352oxc	PDF
CY28352 Abstract: CY28352OC CY28352OCT CY28352OXC Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.	Original	cy28352 ddr400and ddr333-compliant 333-mhz +6400-mhz 200-mhz ddr400-cy28352oc cy28352oct cy28352oxc	PDF
CY28352 Abstract: CY28352OC CY28352OCT CY28352OXC Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features Description • Supports 333 MHz and 400-MHz DDR SDRAM • 60- 200 MHz operating frequency This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.	Original	cy28352 ddr400-ddr333-compliant 400-mhz +3cy28352oc cy28352oct cy28352oxc	PDF
CY28352 Abstract: CY28352OC CY28352OCT Contextual Info: CY28352 Differential Clock Buffer/Driver Features Description • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to six differential outputs • External feedback pin FBIN is used to synchronize	Original	cy28352 28-pin cy28352oc cy28352oct	PDF
CY28352 Abstract: CY28352OC CY28352OCT DDR333 DDR400 Contextual Info: CY28352 Differential Clock Buffer/Driver DDR400- and DDR333 Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications	Original	cy28352 ddr400-ddr333 333-mhz +6400-mhz 200-mhz 28-pin cy28352oc cy28352oct ddr400	PDF