CY7C106 Search Results

Contextual Info: CY7C1069G CY7C1069GE PRELIMINARY 16-Mbit 2 M words x 8 bit Static RAM with Error-Correcting Code (ECC) 16-Mbit (2 M words × 8 bit) Static RAM with Error-Correcting Code (ECC) Features an error indication pin (ERR) that signals the host processor in the case of an ECC error-detection and correction event.

Contextual Info: PRELIMINARY CY7C1061G/CY7C1061GE 16-Mbit 1 M words x 16 bit Static RAM with Error-Correcting Code (ECC) 16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC) Features To access devices with a single chip enable input, assert the chip

Contextual Info: CY7C106A PRELIMINARY y CYPRESS 256K x 4 Static RAM Features Functional D escription • High speed T he CY7C106A is a high-perform ance CM O S static R A M organized as 262,144 words by 4 bits. Easy m em ory expansion is provided by an active LO W chip enable

Contextual Info: CY7C106 ADVANCED INFORMATION CYPRESS SEMICONDUCTOR 262,144 x 4 Static R /W RAM Features Functional Description • High speed - U à = 25 ns T he CY7C106 is a high-performance CMOS static RAM organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW chip enable

Contextual Info: fax id: 1052 W CY7C106 CY7C1006 / C Y P R E S S _ 256K x 4 Static RAM an active LO W o u tp u t enable OE , and th re e -sta te drivers. T h e se devices have an au tom atic pow e r-d ow n fea tu re th a t re­ du ces pow er con sum p tion by m ore than 65% w h e n th e d e vic­

CY7C106A-20VC

Contextual Info: CY7C106A PRELIMINARY 256Kx 4 Static RAM Functional Description Features • H ig h The CY7C106A is a high-performance CMOS static RAM organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW chip enable CE , an active LOW output enable (UE),

C106B4

Abstract: C106B CY7C1006B CY7C106B c106b1 equivalent
Contextual Info: 006B CY7C106B CY7C1006B 256K x 4 Static RAM Features Enable CE , an active LOW Output Enable (OE), and three-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when the devices are deselected.

Contextual Info: CY7C1069DV33 16-Mbit 2 M x 8 Static RAM 16-Mbit (2 M × 8) Static RAM Functional Description Features • High speed ❐ tAA = 10 ns The CY7C1069DV33 is a high performance CMOS Static RAM organized as 2,097,152 words by 8 bits. ■ Low active power ❐ ICC = 175 mA at 100 MHz

CY7C1006D

Abstract: CY7C106D CY7C106D-10VXI 7C106D
Contextual Info: CY7C106D CY7C1006D 1-Mbit 256K x 4 Static RAM Functional Description [1] Features • Pin- and function-compatible with CY7C106B/CY7C1006B • High speed — tAA = 10 ns • Low active power — ICC = 80 mA @ 10 ns • Low CMOS standby power — ISB2 = 3.0 mA

CY7C1061DV33-10BVXI

Abstract: CY7C1061DV33 CY7C1061DV33-10ZXI TSOP 54 thermal resistance CY7C1061 TSOP II 54 Package
Contextual Info: CY7C1061DV33 PRELIMINARY 16-Mbit 1M x 16 Static RAM Features Functional Description • High speed The CY7C1061DV33 is a high-performance CMOS Static RAM organized as 1,048,576 words by 16 bits. — tAA = 10 ns Writing to the device is accomplished by enabling the chip

Contextual Info: PRELIMINARY CY7C1061G/CY7C1061GE 16-Mbit 1 M words x 16 bit Static RAM with Error-Correcting Code (ECC) 16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC) Features To access devices with a single chip enable input, assert the chip

2800-121

Contextual Info: CY7C1061DV18 16-Mbit 1M X 16 Static RAM Features Functional Description • High Speed ❐ tAA = 15 ns The CY7C1061DV18 is a high performance CMOS Static RAM (SRAM) organized as 1,048,576 words by 16 bits. ■ Low Active Power ❐ ICC = 150 mA at 15 ns ■

Contextual Info: CY7C1062DV33 PRELIMINARY 16-Mbit 512K X 32 Static RAM Features Functional Description • High speed The CY7C1062DV33 is a high-performance CMOS Static RAM organized as 524,288 words by 32 bits. — tAA = 10 ns Writing to the device is accomplished by enabling the chip

Contextual Info: CY7C1062DV33 PRELIMINARY 16-Mbit 512K X 32 Static RAM Features Functional Description • High speed The CY7C1062DV33 is a high-performance CMOS Static RAM organized as 524,288 words by 32 bits. — tAA = 10 ns Writing to the device is accomplished by enabling the chip

CY7C1061

Abstract: CY7C1061AV33-12ZI
Contextual Info: CY7C1061AV33 1M x 16 Static RAM Features WE input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through

7C106

Abstract: FE 1.1s
Contextual Info: CY7C106 P R ELIM IN A RY CYPRESS SEMICONDUCTOR 262,144 x 4 Static R/W RAM Features Functional Description • High speed T h e C Y 7 C 1 0 6 is a h ig h -p e rfo rm a n c e C M O S s ta tic R A M o rg a n iz e d a s 262,144 w o rd s by 4 bits. E a sy m e m o ry ex p a n sio n is

CY7C106A

Contextual Info: PRELIMINARY CY7C106A 256K x 4 Static RAM Features D D D D D D The CY7C106A is a highĆperformance CMOS static RAM organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW chip enable CE , an active LOW output enable (OE), and threeĆstate drivers. The device has an

CY7C1069AV33

Contextual Info: CY7C1069AV33 2 M x 8 Static RAM 2 M × 8 Static RAM Features Functional Description • High speed ❐ tAA = 10 ns The CY7C1069AV33 is a high performance complementary metal oxide semiconductor CMOS static RAM organized as 2,097,152 words by 8 bits. Writing to the device is accomplished

CY7C1062DV33

Abstract: IO24
Contextual Info: CY7C1062DV33 16 Mbit 512 K x 32 Static RAM Features Functional Description • High speed ❐ tAA = 10 ns The CY7C1062DV33 is a high performance CMOS Static RAM organized as 524,288 words by 32 bits. ■ Low active power ❐ ICC = 175 mA at 10 ns ■ Low complementary metal oxide semiconductor (CMOS)

CY7C1061BV33-10ZXC

Abstract: CY7C1061BV33 CY7C1061BV33-10ZC CY7C1061BV33-10ZI CY7C1061BV33-12ZXI CY7C1061
Contextual Info: CY7C1061BV33 16-Mbit 1M x 16 Static RAM Features Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into

Contextual Info: CY7C1062DV33 16-Mbit 512K X 32 Static RAM Features Functional Description • High speed ❐ tAA = 10 ns The CY7C1062DV33 is a high performance CMOS Static RAM organized as 524,288 words by 32 bits. ■ Low active power ❐ ICC = 175 mA at 10 ns ■ Low CMOS standby power

7C109A

Abstract: CY7C106A CY7C109 JESD22
Contextual Info: Qualification Report December 1996 QTP# 96053/96081, Version 1.2 1 Meg SRAM - R28 Technology CY7C106A 256K x 4 Static RAM CY7C109 128K x 8 Static RAM PRODUCT DESCRIPTION for qualification Information provided in this document is intended for generic qualification and technically describes the Cypress part

Contextual Info: CY7C1069DV33 16-Mbit 2 M x 8 Static RAM 16-Mbit (2 M × 8) Static RAM Features Functional Description • High speed ❐ tAA = 10 ns The CY7C1069DV33 is a high performance CMOS Static RAM organized as 2,097,152 words by 8 bits. ■ Low active power ❐ ICC = 175 mA at 100 MHz

Contextual Info: CY7C1061AV33 16-Mbit 1 M x 16 Static RAM 16-Mbit (1 M × 16) Static RAM Features Functional Description • High speed ❐ tAA = 10 ns The CY7C1061AV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. ■ Low active power ❐ 990 mW (max)