CY7C1061 Search Results

Contextual Info: PRELIMINARY CY7C1061G/CY7C1061GE 16-Mbit 1 M words x 16 bit Static RAM with Error-Correcting Code (ECC) 16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC) Features To access devices with a single chip enable input, assert the chip

CY7C1061DV33-10BVXI

Abstract: CY7C1061DV33 CY7C1061DV33-10ZXI TSOP 54 thermal resistance CY7C1061 TSOP II 54 Package
Contextual Info: CY7C1061DV33 PRELIMINARY 16-Mbit 1M x 16 Static RAM Features Functional Description • High speed The CY7C1061DV33 is a high-performance CMOS Static RAM organized as 1,048,576 words by 16 bits. — tAA = 10 ns Writing to the device is accomplished by enabling the chip

Contextual Info: PRELIMINARY CY7C1061G/CY7C1061GE 16-Mbit 1 M words x 16 bit Static RAM with Error-Correcting Code (ECC) 16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC) Features To access devices with a single chip enable input, assert the chip

2800-121

Contextual Info: CY7C1061DV18 16-Mbit 1M X 16 Static RAM Features Functional Description • High Speed ❐ tAA = 15 ns The CY7C1061DV18 is a high performance CMOS Static RAM (SRAM) organized as 1,048,576 words by 16 bits. ■ Low Active Power ❐ ICC = 150 mA at 15 ns ■

CY7C1061

Abstract: CY7C1061AV33-12ZI
Contextual Info: CY7C1061AV33 1M x 16 Static RAM Features WE input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through

CY7C1061BV33-10ZXC

Abstract: CY7C1061BV33 CY7C1061BV33-10ZC CY7C1061BV33-10ZI CY7C1061BV33-12ZXI CY7C1061
Contextual Info: CY7C1061BV33 16-Mbit 1M x 16 Static RAM Features Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into

Contextual Info: CY7C1061AV33 16-Mbit 1 M x 16 Static RAM 16-Mbit (1 M × 16) Static RAM Features Functional Description • High speed ❐ tAA = 10 ns The CY7C1061AV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. ■ Low active power ❐ 990 mW (max)

Contextual Info: CY7C1061DV33 16-Mbit 1 M x 16 Static RAM 16-Mbit (1 M × 16) Static RAM Features Functional Description • High speed ❐ tAA = 10 ns The CY7C1061DV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. ■ Low active power ❐ ICC = 175 mA at 100 MHz

Contextual Info: CY7C1061AV33 16-Mbit 1 M x 16 Static RAM 16-Mbit (1 M × 16) Static RAM Features Functional Description • High speed ❐ tAA = 10 ns The CY7C1061AV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. ■ Low active power ❐ 990 mW (max)

CY7C1061AV33-12ZXC

Contextual Info: CY7C1061AV33 1M x 16 Static RAM Features WE input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through

CY7C1061

Abstract: CY7C10612DV33-10ZSXI
Contextual Info: CY7C10612DV33 16-Mbit 1 M x 16 Static RAM Features Functional Description • High speed ❐ tAA = 10 ns The CY7C10612DV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. ■ Low active power ❐ ICC = 175 mA at 10 ns ■

CY7C1061DV33

Abstract: CY7C1061DV33-10BVXI CY7C1061DV33-10ZSXI TSOP II 54 Package CY7C1061 cy7c1061dv33-10bv1xi
Contextual Info: CY7C1061DV33 16-Mbit 1 M x 16 Static RAM Features Functional Description • High speed ❐ tAA = 10 ns The CY7C1061DV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. ■ Low active power ❐ ICC = 175 mA at 10 ns ■ Low CMOS standby power

CY7C1061DV33-10BV1XI

Abstract: cy7c1061dv33 10bv BV1X BVJ 47
Contextual Info: CY7C1061DV33 16-Mbit 1 M x 16 Static RAM 16-Mbit (1 M × 16) Static RAM Features Functional Description • High speed ❐ tAA = 10 ns The CY7C1061DV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. ■ Low active power ❐ ICC = 175 mA at 100 MHz

CY7C1061

Contextual Info: CY7C10612DV33 16-Mbit 1 M x 16 Static RAM 16-Mbit (1 M × 16) Static RAM Features Functional Description • High speed ❐ tAA = 10 ns The CY7C10612DV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. ■ Low active power

CY7C1061AV33

Abstract: CY7C1061AV33-10BAC CY7C1061AV33-10BAXI CY7C1061AV33-10ZI CY7C1061AV33-10ZXC CY7C1061AV33-10ZXI CY7C1061AV33-12ZC CY7C1061AV33-12ZXC CY7C1061AV
Contextual Info: CY7C1061AV33 16-Mbit 1M x 16 Static RAM Features Functional Description • High speed The CY7C1061AV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. — tAA = 10 ns • Low active power To write to the device, enable the chip (CE1 LOW and CE2

Contextual Info: CY7C1061AV33 16-Mbit 1M x 16 Static RAM Features Functional Description • High speed The CY7C1061AV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. — tAA = 10 ns • Low active power To write to the device, enable the chip (CE1 LOW and CE2

CY7C1061

Abstract: 54-pin TSOP thermal resistance junction to case
Contextual Info: CY7C1061BV33 16-Mbit 1M x 16 Static RAM Features Functional Description • High speed The CY7C1061BV33 is a high-performance CMOS Static RAM organized as 1,048,576 words by 16 bits. — tAA = 8, 10, 12 ns Writing to the device is accomplished by enabling the chip (CE

CY7C1061

Contextual Info: CY7C1061DV33 PRELIMINARY 16-Mbit 1M x 16 Static RAM Features Functional Description • High speed The CY7C1061DV33 is a high-performance CMOS Static RAM organized as 1,048,576 words by 16 bits. — tAA = 10 ns Writing to the device is accomplished by enabling the chip

Contextual Info: CY7C1061DV33 16-Mbit 1M x 16 Static RAM Features Functional Description • High speed ❐ tAA = 10 ns The CY7C1061DV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. ■ Low active power ❐ ICC = 175 mA at 10 ns ■ Low CMOS standby power

CY7C1061AV25

Abstract: CY7C1061AV25-8ZC CY7C1061AV25-8ZI CY7C1061A CY7C1061AV25-10BAI
Contextual Info: CY7C1061AV25 PRELIMINARY 1M x 16 Static RAM Features specified on the address pins A0 through A19 . If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19).

CY7C1061DV33

Abstract: CY7C1061DV33-10BVXI CY7C1061DV33-10ZSXI
Contextual Info: CY7C1061DV33 16-Mbit 1M x 16 Static RAM Features Functional Description • High speed ❐ tAA = 10 ns The CY7C1061DV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. ■ Low active power ❐ ICC = 175 mA at 10 ns ■ Low CMOS standby power

CY7C1061

Abstract: CY7C1061AV33 CY7C1061AV33-8ZC CY7C1061AV33-8ZI CY7C1061AV33-8BAI CY7C1061AV33-12ZI
Contextual Info: CY7C1061AV33 1M x 16 Static RAM Features specified on the address pins A0 through A19 . If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). • High speed

CY7C1061AV33

Abstract: CY7C1061AV33-10BAC CY7C1061AV33-10BAXI CY7C1061AV33-10ZI CY7C1061AV33-10ZXC CY7C1061AV33-10ZXI CY7C1061AV33-12ZC CY7C1061AV33-12ZXC CY7C1061
Contextual Info: CY7C1061AV33 16-Mbit 1M x 16 Static RAM Features Functional Description • High speed The CY7C1061AV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. — tAA = 10 ns • Low active power To write to the device, enable the chip (CE1 LOW and CE2

Contextual Info: CY7C10612G CY7C10612GE PRELIMINARY 16-Mbit 1 M x 16 Static RAM 16-Mbit (1 M × 16) Static RAM Features • High speed ❐ tAA = 10 ns ■ Embedded error-correcting code (ECC) for single bit error correction ■ Low active power ❐ ICC = 90mA typical ■