7C601 Search Results

M 4 3171

Contextual Info: ABACUS 3171 FLOATING-POINT COPROCESSOR FOR SPARC PRELIMINARY DATA August 1989 Features DIRECT INTERFACE TO MEMORY 25, 33, A N D 40 M H Z OPERATION FULL COM PLIANCE W ITH A N SI/IE E E -754 STANDARD FOR BINARY FLOATING-POINT ARITHM ETIC 143-PIN PGA PACKAGE

CY7C601

Abstract: CY7C600 7C600 CY7C157A
Contextual Info: • - ^ SEMICONDUCTOR Introduction to RISC and com piler design. A t each step, com puter architects must ask: to what extent does a feature improve o r degrade perform ance and is it w orth the cost of im plem entation? Each additional feature, no m atter how useful it is in an isolated instance, makes all others p er­

CYM6002K

Abstract: CY7C605 Cy7C601 AD31J 1RL0
Contextual Info: PR ELIM INARY CYM6002K CYPRESS SEMICONDUCTOR SPARCore Dual-CPU Module Features * Complete SPARC® Dual-CPU mod­ ule, including cache — TWo 7C601 Integer Units IU — Two CY7C602 Floating-Point Units (FPU) — Two CY7C605 Cache Controller and Memory M anagement Units

Contextual Info: Data Sheet February 1992 ATT7C157 m A T& T Microelectronics High-Speed CMOS Cache SRAM 256 Kbit 16K x 16 RISC-Based, Self-Timed, Latched Data I/O Features High speed — 15 ns maximum access time TTL compatible inputs and outputs Easy interface with SPARC' RISC architecture

Contextual Info: CYPRESS MbE D SEMICONDUCTOR ^ asa-Ttta oao74t.i T - M i- n - 3 8 CYPRESS SEMICONDUCTOR • Reduced Instruction Set Computer RISC Architecture — Simple format instructions — M ost instructions execute in a single cycle • Very high performance — 25-, 33-, and 40-MHz clock speeds

CY7C601

Abstract: CY7C601A bicc CY7C602A WORD11
Contextual Info: 7C601A CYPRESS SEMICONDUCTOR Features • Reduced Instruction Set Computer RISC Architecture — Simple format instructions — Most instructions execute in a single cycle • Very high performance — 25-, 33*, and 40-MHz clock speeds yield 18,24, and 29 MIPS sustained

7C601

Abstract: C32S CY7C325 C3253
Contextual Info: PRELIMINARY £25 CYPRESS SEMICONDUCTOR • Timing Control Unit, Clock Genera­ tor for 7C601A and CY7C611A SPARC processors • Supports 25-, 33-, 40-MHz operation • Simplifies interface to slow memory and peripherals by eliminating the need for wait-state logic

6j15

Contextual Info: CY7C277 CY7C279 CYPRESS SEMICONDUCTOR Reprogrammable 32,768 x 8 Registered PROM Features • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 30 ns max set-up — 15 ns dock to output Programmable address latch enable input

90c61

Abstract: Trap floating point
Contextual Info: 4 CIE D MATRA M H S • SñbñMSb 00023^^ _ F p B A f C lllììlilll I w T B W 414 «M M H S _ " 3 8 January 1991 90C601 DATA SHEET_ 32-BIT RISC PROCESSOR FEATURES ■ REDUCED INSTRUCTION SET COMPUTER RISC ARCHITECTURE - SIMPLE FORMAT INSTRUCTIONS

CY7C601

Contextual Info: " ^ ^ 5 jF CY7C604A _ - _ - . - - - • - Cache Controller and Memory Management Unit CYPRESS — SEMICONDUCTOR Features • Fully conforms to the SPARC Reference Memory M anagement Unit M M U Architecture • Hardware table walk Description

TAG scr Selection Guide

Abstract: CY7C604
Contextual Info: CYPRESS SEMICONDUCTOR 4bE D m asa^bbs 0007475 1 ^ 5 3 - - 3 3 - a .S T CYPRESS SEMICONDUCTOR • Fully conforms to the SPARC Refer­ ence Memory Management Unit MMU Architecture • Support for virtual memory • Supports context snitching — 4096 contexts for TLB entries

ci 7495

Abstract: capacitor 107 16k 7C602 ATT7C157M-20 att cache
Contextual Info: HAR . ja;* Data Sheet February 1992 ATT7C157 m A T& T M icroelectronics High-Speed CMOS Cache SRAM 256 Kbit 16K x 16 RISC-Based, Self-Timed, Latched Data I/O Features High speed — 15 ns maximum access time TTL compatible inputs and outputs Easy interface with SPARC* RISC architecture

Cy7C601

Abstract: D6336 7C605
Contextual Info: CY7C605A r ^ p p rc c SEMICONDUCTOR Features • M ultiprocessing support • Pin-compatible with CY7C604A • Cache coherency protocol modeled af­ ter IEEE Futurebus • Separate virtual and physical cache tag memories — Each cache tag memory holds 2048

F7307

Contextual Info: CY7C277 CY7C279 CYPRESS SEMICONDUCTOR Features • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 30 ns 7C277 and 3 ns (7C279) max. set-up — 15 ns (7C277) and 35 ns (7C279) clock to output • Low power — 660 mW (commercial)

7C602

Abstract: CY7C601
Contextual Info: CY7C602A CYPRESS SEMICONDUCTOR Features • Direct interface to 7C601 integer unit • Direct interface to CY7C157 Cache Storage Unit CSU • FullcompliancewithANSI/IEEE-754 standard for binary floating-point arithmetic • Supports single and double precision

aj4 diode

Abstract: CY7C277 658f 7C277
Contextual Info: CYPRESS 4bE SEMICONDUCTOR J /s S - I SSfl'lbbS GG0bôb3 fl B C Y P D CY7C277 CY7C279 CYPRESS SEMICONDUCTOR Reprogrammable 32K x 8 Registered PROM Programmable address latch enable input Programmable synchronous or asynchronous output enable 7C277 On-chip edge-triggered output

cy7c611

Abstract: CY7C602A asi cypress CY7C157A CY7C611A 38R1
Contextual Info: CY7C611A CYPRESS SEMICONDUCTOR Features • SPARC CD processor optimized for em­ bedded control applications • Reduced Instruction Set Computer RISC architecture — Simple format instructions — M ost instructions execute in a single cycle • Very high performance

Contextual Info: CY7C277 CY7C279 CYPRESS SEMICONDUCTOR Features Reprogrammable 32K x 8 Registered PROM Programmable address latch enable input Programmable synchronous or asynchronous output enable 7C277 On-chip edge-triggered output registers (7C277) Optional registered/latched address

JTAG MIPS

Abstract: Cy7C601 cy7c602 6001K 7C601 CY7C604
Contextual Info: r PRELIM INARY CYPRESS SEMICONDUCTOR CYM6001K = SPARCore CPU Module Features • Available at 2 5 ,33, and 40 MHz Functional Description • Complete SPARC® CPU solution, includingcache • Each SPARCore module features: — SPARC integer and floating-point

CY7C601

Abstract: cccv
Contextual Info: 7C601A r ^ y p p r c c • — 32-Bit RISC Processor SEMICONDUCTOR — R egisters can be u sed a s e ight w in­ dows o f 24 registers each for low pro ced u re overhead Features • Reduced In stru c tio n Set C om puter R ISC A rchitecture — Sim ple fo rm at in stru ctio n s

Contextual Info: Dats Sheet January 1992 ATT7C157 - ATo.T - — M lo il Microelectronics High-Speed CMOS Cache SRAM 256 Kbit 16K x 16 RISC-Based, Self-Timed, Latched Data I/O Features • High-speed— 15 ns maximum access time ■ TTL compatible inputs and outputs ■ Advanced CMOS technology

powerful listening bug abstract

Abstract: powerful listening bug XAPP1137 ML507 PPC440 powerpc 464 GPR16 buggy 5156k 871265
Contextual Info: Application Note: Embedded Processing R XAPP1137 v1.0 June 9, 2009 Linux Operating System Software Debugging Techniques with Xilinx Embedded Development Platforms Author: Brian Hill Abstract This application note discusses Linux Operating System debugging techniques. Debugging

CY7C157A

Contextual Info: 7C601A CYPRESS SEMICONDUCTOR 32-Bit RISC Processor — Registers can be used as eight win­ dows of 24 registers each for low procedure overhead — Registers can also be used as regis­ ter banks for fast context switching Features • Reduced Instruction Set Computer

Cy7C601

Abstract: CY7C605 c5wg
Contextual Info: 4t.E D CYPRESS SEMICONDUCTOR El H S Ö i L b a 0 0 0 7 4 0 4 S S3 CYP CY7C605A -_-ra ¿rar y — zr^r CYPRESS SEMICONDUCTOR Features Cache Controller and Memory Management Unit Fully conforms to the SPARC refer­ ence M emory M anagement Unit M M U architecture