7C157A Search Results

j6920

Contextual Info: 7C157A CYPRESS SEMICONDUCTOR Features Functional Description • Optimized for use with RISC proces­ sors, including SPARC • Address and WE registers • CMOS for optimum speed/power • High speed — 18 ns T h e C Y 7C157A cache storage u n it is a

Contextual Info: 7C157A CYPRESS SEMICONDUCTOR Features Functional Description • Optimized for use with RISC proces­ sors, including SPARC • Address and WE registers • CMOS for optimum speed/power • High speed — 18 ns T h e C Y 7C157A cache storage u n it is a

CY7C157A

Abstract: C1572 7C600
Contextual Info: 7C157A JS r ' v p p r c c W SEMICONDUCTOR Features Functional Description • Optimized for use with RISC procès* sors, including SPARC The CY 7C157A cache storage unit is a high-perform ance CM O S static R A M o r­ ganized as 16,384 x 16 bits. It is optim ized

CY7C601

Abstract: CY7C600 7C600 CY7C157A
Contextual Info: • - ^ SEMICONDUCTOR Introduction to RISC and com piler design. A t each step, com puter architects must ask: to what extent does a feature improve o r degrade perform ance and is it w orth the cost of im plem entation? Each additional feature, no m atter how useful it is in an isolated instance, makes all others p er­

j6920

Abstract: CY7C600
Contextual Info: CYPRESS SEMICONDUCTOR MbE D O SSÔTbbS □□□bLf33 S Z I CYP v CYPRESS -­ SEMICONDUCTOR 7C157A 16,384 x 16 Static R/W Cache Storage Unit Features Ebnctional Description • Optimized for use with RISC proces­ sors, Including SPARC • Address and WE registers

CY7C157A

Contextual Info: 7C157A 16,384 x 16 Static R/W Cache Storage Unit PRELIMINARY CYPRESS _ SEMICONDUCTOR Features • Optimized for use with CY7C600 SPARC product family • Address and WE registers • CMOS for optimum speed/power • High speed - 2 0 ns • Data In and Data Out latches

CY7C601

Contextual Info: " ^ ^ 5 jF CY7C604A _ - _ - . - - - • - Cache Controller and Memory Management Unit CYPRESS — SEMICONDUCTOR Features • Fully conforms to the SPARC Reference Memory M anagement Unit M M U Architecture • Hardware table walk Description

Cy7C601

Abstract: D6336 7C605
Contextual Info: CY7C605A r ^ p p rc c SEMICONDUCTOR Features • M ultiprocessing support • Pin-compatible with CY7C604A • Cache coherency protocol modeled af­ ter IEEE Futurebus • Separate virtual and physical cache tag memories — Each cache tag memory holds 2048

CY7C611

Contextual Info: CY7C611A CYPRESS SEMICONDUCTOR Features • SPARC processor optimized for em­ bedded control applications 32-Bit RISC Controller 136 32-bit registers — Eight overlapping windows o f 24 registers each — Dividing registers into seperate register banks allows fast context

cy7c611

Abstract: CY7C602A asi cypress CY7C157A CY7C611A 38R1
Contextual Info: CY7C611A CYPRESS SEMICONDUCTOR Features • SPARC CD processor optimized for em­ bedded control applications • Reduced Instruction Set Computer RISC architecture — Simple format instructions — M ost instructions execute in a single cycle • Very high performance

CY7C601

Abstract: cccv
Contextual Info: CY7C601A r ^ y p p r c c • — 32-Bit RISC Processor SEMICONDUCTOR — R egisters can be u sed a s e ight w in­ dows o f 24 registers each for low pro ced u re overhead Features • Reduced In stru c tio n Set C om puter R ISC A rchitecture — Sim ple fo rm at in stru ctio n s

C1576

Contextual Info: CYPRESS MbE D SEMICONDUCTOR SSñRbbE D DG b L f 33 S D CYP 7C157A CYPRESS SEMICONDUCTOR Features Functional Description • O ptim ized for u se w ith R IS C p ro ces­ so rs, Includin g SPARC T h e C Y 7C 157A cach e sto rag e u n it is a hig h-perform ance C M O S static R A M o r ­