CY7C157A Search Results

j6920

Abstract: CY7C600
Contextual Info: CYPRESS SEMICONDUCTOR MbE D O SSÔTbbS □□□bLf33 S Z I CYP v CYPRESS -­ SEMICONDUCTOR CY7C157A 16,384 x 16 Static R/W Cache Storage Unit Features Ebnctional Description • Optimized for use with RISC proces­ sors, Including SPARC • Address and WE registers

CY7C157A

Contextual Info: CY7C157A 16,384 x 16 Static R/W Cache Storage Unit PRELIMINARY CYPRESS _ SEMICONDUCTOR Features • Optimized for use with CY7C600 SPARC product family • Address and WE registers • CMOS for optimum speed/power • High speed - 2 0 ns • Data In and Data Out latches

j6920

Contextual Info: CY7C157A CYPRESS SEMICONDUCTOR Features Functional Description • Optimized for use with RISC proces­ sors, including SPARC • Address and WE registers • CMOS for optimum speed/power • High speed — 18 ns T h e C Y 7C157A cache storage u n it is a

C1576

Contextual Info: CYPRESS MbE D SEMICONDUCTOR SSñRbbE D DG b L f 33 S D CYP CY7C157A CYPRESS SEMICONDUCTOR Features Functional Description • O ptim ized for u se w ith R IS C p ro ces­ so rs, Includin g SPARC T h e C Y 7C 157A cach e sto rag e u n it is a hig h-perform ance C M O S static R A M o r ­

Contextual Info: CY7C157A CYPRESS SEMICONDUCTOR Features Functional Description • Optimized for use with RISC proces­ sors, including SPARC • Address and WE registers • CMOS for optimum speed/power • High speed — 18 ns T h e C Y 7C157A cache storage u n it is a

CY7C157A

Abstract: C1572 7C600
Contextual Info: CY7C157A JS r ' v p p r c c W SEMICONDUCTOR Features Functional Description • Optimized for use with RISC procès* sors, including SPARC The CY 7C157A cache storage unit is a high-perform ance CM O S static R A M o r­ ganized as 16,384 x 16 bits. It is optim ized

CY7C601

Abstract: CY7C600 7C600 CY7C157A
Contextual Info: • - ^ SEMICONDUCTOR Introduction to RISC and com piler design. A t each step, com puter architects must ask: to what extent does a feature improve o r degrade perform ance and is it w orth the cost of im plem entation? Each additional feature, no m atter how useful it is in an isolated instance, makes all others p er­

Contextual Info: CYPRESS MbE D SEMICONDUCTOR ^ asa-Ttta oao74t.i T - M i- n - 3 8 CYPRESS SEMICONDUCTOR • Reduced Instruction Set Computer RISC Architecture — Simple format instructions — M ost instructions execute in a single cycle • Very high performance — 25-, 33-, and 40-MHz clock speeds

CY7C601

Abstract: CY7C601A bicc CY7C602A WORD11
Contextual Info: CY7C601A CYPRESS SEMICONDUCTOR Features • Reduced Instruction Set Computer RISC Architecture — Simple format instructions — Most instructions execute in a single cycle • Very high performance — 25-, 33*, and 40-MHz clock speeds yield 18,24, and 29 MIPS sustained

CY7C601

Contextual Info: " ^ ^ 5 jF CY7C604A _ - _ - . - - - • - Cache Controller and Memory Management Unit CYPRESS — SEMICONDUCTOR Features • Fully conforms to the SPARC Reference Memory M anagement Unit M M U Architecture • Hardware table walk Description

TAG scr Selection Guide

Abstract: CY7C604
Contextual Info: CYPRESS SEMICONDUCTOR 4bE D m asa^bbs 0007475 1 ^ 5 3 - - 3 3 - a .S T CYPRESS SEMICONDUCTOR • Fully conforms to the SPARC Refer­ ence Memory Management Unit MMU Architecture • Support for virtual memory • Supports context snitching — 4096 contexts for TLB entries

7C602

Abstract: CY7C601
Contextual Info: CY7C602A CYPRESS SEMICONDUCTOR Features • Direct interface to CY7C601 integer unit • Direct interface to CY7C157 Cache Storage Unit CSU • FullcompliancewithANSI/IEEE-754 standard for binary floating-point arithmetic • Supports single and double precision

CY7C157A

Contextual Info: CY7C601A CYPRESS SEMICONDUCTOR 32-Bit RISC Processor — Registers can be used as eight win­ dows of 24 registers each for low procedure overhead — Registers can also be used as regis­ ter banks for fast context switching Features • Reduced Instruction Set Computer

Cy7C601

Abstract: CY7C605 c5wg
Contextual Info: 4t.E D CYPRESS SEMICONDUCTOR El H S Ö i L b a 0 0 0 7 4 0 4 S S3 CYP CY7C605A -_-ra ¿rar y — zr^r CYPRESS SEMICONDUCTOR Features Cache Controller and Memory Management Unit Fully conforms to the SPARC refer­ ence M emory M anagement Unit M M U architecture

Cy7C601

Abstract: STD-745-1985 cy7c601a
Contextual Info: CY7C602A CYPRESS SEMICONDUCTOR Features • Direct interface to CY7C601 integer unit • Direct interface to CY7C157 Cache Storage Unit CSU • Full compliance with ANSI/IEEE-754 standard for binary floating-point arithmetic • Supports single and double precision

CY7C157A

Contextual Info: CY7C611A CYPRESS SEMICONDUCTOR Features • SPARC processor optimized for em ­ bedded control applications 32-Bit RISC Controller — Privileged instructions • 136 32-bit registers — Eight overlapping windows o f 24 registers each • Artificial intelligence support