CY7C605 Search Results

CYM6002K

Abstract: CY7C605 Cy7C601 AD31J 1RL0
Contextual Info: PR ELIM INARY CYM6002K CYPRESS SEMICONDUCTOR SPARCore Dual-CPU Module Features * Complete SPARC® Dual-CPU mod­ ule, including cache — TWo CY7C601 Integer Units IU — Two CY7C602 Floating-Point Units (FPU) — Two CY7C605 Cache Controller and Memory M anagement Units

CY7C605

Abstract: CY7C602 Cy7C601 MADJ IrL 1520 N M-BUS CYM6003K
Contextual Info: CYM6003K PRELIMINARY CYPRESS SEMICONDUCTOR Features • Complete SPARC CPU solution including cache — CY7C601 Integer Unit iU — CY7C602 Floating-Point Unit (FPU) — CY7C605 Cache Controller and Memory Management Unit for Multiprocessing (CMU - MP)

Contextual Info: 4. Incremental ADC Incremental ADC Data Sheet ADCINC Copyright 2008 Cypress Semiconductor Corporation. All Rights Reserved. Resources CY8C20x66, CY7C643/4/5xx, CY7C60424, CY7C6053x, CYONS2xxx, CYONS2xLx PSoC Blocks API Memory CapSense I2C/SPI Timer Comparator

CY8C20x66

Contextual Info: 4. Incremental ADC Incremental ADC Data Sheet ADCINC Copyright 2008-2009 Cypress Semiconductor Corporation. All Rights Reserved. Resources PSoC Blocks CapSense I2C/SPI Timer API Memory Comparator Flash RAM Pins per External IO CY8C20x66, CY8C20x46, CY8C20x96, CY7C643/4/5xx, CY7C60424, CY7C6053x, CYONS2xxx, CYONS2xLx,

Cy7C601

Abstract: D6336 7C605
Contextual Info: CY7C605A r ^ p p rc c SEMICONDUCTOR Features • M ultiprocessing support • Pin-compatible with CY7C604A • Cache coherency protocol modeled af­ ter IEEE Futurebus • Separate virtual and physical cache tag memories — Each cache tag memory holds 2048

Cy7C601

Abstract: CY7C605 c5wg
Contextual Info: 4t.E D CYPRESS SEMICONDUCTOR El H S Ö i L b a 0 0 0 7 4 0 4 S S3 CYP CY7C605A -_-ra ¿rar y — zr^r CYPRESS SEMICONDUCTOR Features Cache Controller and Memory Management Unit Fully conforms to the SPARC refer­ ence M emory M anagement Unit M M U architecture

Contextual Info: 10. Comparator Comparator Data Sheet CMP vX.Y Copyright 2001-2008. Cypress Semiconductor. All Rights Reserved. PSoC Blocks Resources CapSense CY8C20x34, CY8C20x24, CY8C20x66, CY7C643xx, CY7C604xx, CYONS2xxx, CYONS2xLx I2C/SPI API Memory Bytes Timer

CY7C601

Abstract: CY7C600 7C600 CY7C157A
Contextual Info: • - ^ SEMICONDUCTOR Introduction to RISC and com piler design. A t each step, com puter architects must ask: to what extent does a feature improve o r degrade perform ance and is it w orth the cost of im plem entation? Each additional feature, no m atter how useful it is in an isolated instance, makes all others p er­

Contextual Info: 10. Comparator Comparator Data Sheet CMP Copyright 2001-2008 Cypress Semiconductor Corporation. All Rights Reserved. PSoC Blocks Resources CapSense CY8C20x34, CY8C20x24, CY8C20x66, CYONS2xxx, CYONS2xLx I2C/SPI API Memory Bytes Timer X Flash ±3% RAM

F4T5

Abstract: selectronic MAD45 csta 020 26
Contextual Info: M l WHS electronic June 1992 90C600 HI-REL DATA SHEET The 90C600 chip-set is a 32-bit custom CMOS implementation of the SPARCT architecture. The 90C600 CPU includes the 90C601 Integer Unit IU , the 90C602 Floating-Point Unit (FPU), the 90C604 Cache controller and MMU (CMU),