54S112 Search Results

Contextual Info: LS73 LS76 LS107 LS112 Dual J-K Negative-Edge-Triggered Flip-Flops LS113 •Pin-for-Pin and functional equivalents to 5473, 5476, 54107, 54S112, 54S113 PIN-OUT DIAGRAMS DESCRIPTION These monolithic dual J-K flip-flops feature individual J, K, clock, and asynchronous preset and clear inputs to each

54S112

Abstract: totempole d2302
Contextual Info: Signetics 54S 112 Flip-Flop Dual J-K Edge-Triggered Flip-Flop Product Specification Military Logic Products DESCRIPTION The 54S112 is a dual J-K negative edge-triggered flip-flop featuring individu­ al J, K, Clock, Set and Reset inputs. The Set 5d and Reset (RD) inputs, when Low,

74S112

Abstract: 54S112 ScansUX1001
Contextual Info: FAIRCHILD SUPER HIGH SPEED TTL/SSI • 9S112/54S112, 74S112 DUAL JK EDGE-TRIGGERED FLIP-FLOP DESCRIPTION — The 9S112/54S 112, 74S112 dual J K flip -flo p s feature individual J, K, clock, and asynchronous preset and clear inputs to each flip -flo p . When the clock goes H IG H , the inputs are enabled and data w ill be accepted. The logic level o f the J and K inputs may be

LS107

Abstract: LS112 LS76 LS113 54S112 54S113 LS73 raytheon 74
Contextual Info: LS73 LS76 LS107 LS112 Dual J-K Negative-Edge-Triggered Flip-Flops _ LS113 •Pin-for-Pin and functional equivalents to 5473, 5476, 54107, 54S112, 54S113 P IN -O U T D IA G R A M S DESCRIPTION Th e se m o n o lith ic dual J -K flip -flo p s fe a tu re in d iv id u a l J, K ,

dy 255

Abstract: 74s405 H R C M F 2J 225 Fairchild 9960 nixie driver 9614 line driver ci 8602 gn block diagram FJH211 Fairchild msi cul9960 variable frequency circuit diagram using IC 555
Contextual Info: IN THE, BOSTON - 6 17- 4 4 * A SUBSIDiA) ./ OF DUCOMMUN INCORPOfiATED S, MASS vw . JU N E 1 97 S Fairchild Semiconductor TTL Data Book Contents And Section Selector If you know the correct 5400, 7400, 9300 or 9600 device type number, find the correct page in the

74s112n

Abstract: 54S112 74S112
Contextual Info: I R C H I L D S E M I C O N D U C T O R TM DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description sition tim e of th e negative going edge o f the clock pulse. Data on the J and K inputs can be changed w hile the clock

74s188 programming

Abstract: 74S471 N82S06 74S470 dip18 package str 52100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 74S472 PROM PROGRAMMING 8080a 74S287 programming instructions
Contextual Info: The E ngineering Staff of TEXAS INSTRUMENTS INCORPORATED Semiconductor Memory Data Book y for \ T exas In Design Engineers s t r u m e n t s >le of Contents • Alphanumeric Index • GENERAL INFORMATION Selection Guides • Glossary INTERCHANGEABILITY GUIDE

itt 7441

Abstract: transistor fcs 9012 7446 BCD to 7-segment Fairchild dtl catalog Truth Table 74192 7400 quad 2-input NAND gate truth-table 7449 BCD to 7-segment 7483 truth table Motorola Diode 54H01 semiconductors cross reference
Contextual Info: TTL DATA BOOK Fairchild Semiconductor TTL Data Book Contents And Section Selector If you know the correct 5400, 7400, 9300 or 9600 device type number, find the correct page in the Numerical Index. If you are trying to choose the best device for your application, consult the

SN74ALS123

Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
Contextual Info: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS

SN7449

Abstract: 54175 SN7401 74L42 SN7437 SN74S40
Contextual Info: Ordering Instructions and Mechanical Data INTEGRATED CIRCUITS MECHANICAL DATA ORDERING INSTRUCTIONS Electrical characteristics presented in this catalog, unless otherwise noted, apply for circuit type s listed in the page heading regardless of package. Except for diode arrays, ECL, and MOS devices, the availability of a circuit function in a

bipolar PROM

Abstract: plhs18p8 S4LS04 82HS641 PLHS18 54175 82s137a 82S191 68172 54F04
Contextual Info: Signetics I Alphanumeric I Index Military Products H LM119 LM124 LM139 Vol. 1 17 Dual Voltage Comparator Vol.2 22 26 26 Low Power Quad Op Amp LM139A Qual Voltage Comparator Qual Voltage Comparator PLC18V8Z Zero Standby Power Universal PAL -Type Device PLC415

54s112

Abstract: 74LS112A 74S112
Contextual Info: SN54LS112A, 54S112, SN74LS112A. SN74S112A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR _ Fully Buffered to Offer Maximum Isolation from External Disturbance • D 2 6 6 1 . A P R IL 1 9 8 2 - R E V I S E D M A R C H 1 9 8 8

LG color tv Circuit Diagram schematics

Abstract: texas ttl YJ 162A Texas Instruments TTL integrated circuits catalog SN74180 AC digital voltmeter using 7107 Sii 9024 MC3123 sn74ls860 SN7490AJ sn74243
Contextual Info: IN D EXES Alphanumeric • Functional/Selection Guide IN T E R C H A N G E A B ILIT Y GUIDE G E N E R A L INFORM ATION O RD ERIN G IN STRUCTIO N S AND M ECH A N ICA L D A TA 5 4 /7 4 FA M ILIE S OF CO M PATIBLE T T L C IR C U ITS 54/74 F A M IL Y SSI C IR C U ITS

Contextual Info: 112 CONNECTION DIAGRAM P IN O U T A 54S/74S112 t1" 00 \/&4LS/74LS112 b DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION — The '112 features individual J, K, C lo ck and asynchronous Set and C lear inputs to each flip-flop. When the clo ck goes HIGH, the inputs

54S38

Abstract: SN74298 SN74265 54175 NES 1004 naval specification 74L95 Transistor AF 138 07802-1 SN7437 SN54LS195A
Contextual Info: m - G EN ER A L IN F O R M A TIO N INDEXES Numerical • Functional/Selection Guide O R D E R IN G INSTRUCTIO NS A N D M E C H A N IC A L D ATA 1 1 5 4/74 F A M IL Y SSI C IR CU ITS 2 I 54/74 F A M IL Y M S I/LSI C IR C U ITS 3 S E R IE S 29000 S S I C IR C U IT S

LS112A

Abstract: SN54LS112 SN54LS112A SN54S112 SN74 SN74LS112A SN74S112A
Contextual Info: SN5 4 L S 112A, SN5 4 S 112, SN7 4 L S 112A, SN7 4 S 112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS WITH PRESET AND CLEAR D 2 6 6 1 . A P R IL 1 9 8 2 - R E V IS E D M A R C H 1 9 8 8 Fully Buffered to Offer Maximum Isolation from External Disturbance S N 5 4 L S 1 1 2 A . S N 5 4 S 1 1 2 . . . J OR W P A C K A G E

ay-5-1012

Abstract: ali m 3329 PROCESSOR ALI 3329 ali 3329 b ali 3329 SN74188 sn74s188 str 52100 SN7452 replacement of bel 187 transistor
Contextual Info: GENERAL INFORMATION lie of Contents • Alphanumeric Index • Selection Guides • Glossary INTERCHANGEABiliTY GUIDE MOS MEMORIES TTL MEMORIES ECl MEMORIES MICROPROCESSOR SUMMARY 38510/MACH IV PROCUREMENT SPECIFICATION JAN Mll-M-38510 INTEGRATED CIRCUITS

m38510/06301

Abstract: M38510-06302 m38510 m38510/20702 M38510/00801 M38510/00104 m38510/01201 M38510/20802 82S62 M38510/01302
Contextual Info: JAN/SMD Devices JAN/SMD Source JAN/SMD Source JAN/SMD Source M38510/00101 5430 M38510/07701 54S138 M38510/31512 54LS163A M38510/00102 5420 M38510/07702 54S139 M38510/31601 54LS75 M38510/00103 5410 M38510/07801 54S181 M38510/31603 54LS259 M38510/00104 5400

IC 74151 diagram and truth table

Abstract: 7474 ic 2x4 demultiplexer using ic 74155 EQUIVALENT 9974 GP 7447 BCD to 7-segment APPLICATION NOTES CD 7474 IC IC 7404 7406 truth table bcd vm 170 1p0 8-input 7430 NAND gate with truth table 7448 bcd to seven segment decoder
Contextual Info: TTL DATA BO O K Fairchild Semiconductor TTL Data Book Contents And Section Selector If you know the correct 5400, 7400, 9300 or 9600 device type number, find the correct page in the Numerical Index. If you are trying to choose the best device for your application, consult the

74S112N

Contextual Info: R C H U - P S E M IC O N D U C T O R tm DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description sition tim e of th e negative going edge o f the clock pulse. Data on the J and K inputs can be changed w hile the clock

SN74LS112

Abstract: SN54LS112A SN54S112 SN74LS112A SN74S112A SN54L5112A 5S012
Contextual Info: SN54LS112A, 54S112, SN74 LS112A , SN74 S 112 A D U A L J-K NE GAT IVE EDGE-TRIGGERED FLIP FLO P S WITH PR ESE T AN D CLEA R SDLS011 D 2 6 6 1 , APRIL 1 9 8 2 —REVISED M A R C H 1 9 8 8 • Fully Buffered to Offer Maximum Isolation from External Disturbance

JD 1803

Abstract: jd 1803 IC jd 1803 data sheet SNV55LVDS31W SNV55LVDS32W jd 1803 data SMV320C6701GLPW14 54LS74A bistable multivibrator using ic 555 SNV54LVTH162245WD
Contextual Info: Mil Sel Guide 04-home-new.qxd R 8/11/2004 2:21 PM E A L W Page 1 O R L D S I G N A L P TM R O C E S S I N G Military Semiconductors Selection Guide 2004-2005 Mil Sel Guide 04-home-new.qxd 8/11/2004 2:21 PM Page 2 Table of Contents and Introduction Enhanced Plastic

2650B

Abstract: wf vqc 10d alu 9308 d Signetics 2650 SN52723 2650 cpu 82S103 pipbug Signetics NE561 cd 75232
Contextual Info: flcnCTICf ßii>ouiR/mos fflICROPROCEÍSOR DATfl mnnuni SIGNETICS reserves the right to make changes in the products contained in this book in order to improve design or performance and to supply the best possible products. Signetics also assumes no responsibility for the

1n52408

Abstract: 1N52428 zener SFC2311 78M12HM 21L02A 54175 IRS 9530 transistor 10116dc BB105G 962PC
Contextual Info: Contents Fairchild Semiconductors Ltd. Solid State Scientific Inc. Diodes Ltd. Thomson C. S. F. B Ashcroft Electronics Ltd. Sprague Electric UK Ltd. Precision Dynamic Corp. B&R Relays Schrack Relays Heller mann Electric B Foreword We are pleased to present the latest edition of the BARLEC Catalogue, which