54LS27 Search Results

LS279

Abstract: 54LS279 54LS279DMQB 54LS279FMQB 54LS279LMQB DM54LS279 DM54LS279J DM74LS279 DM74LS279M DM74LS279N
Contextual Info: 54LS279 54LS279 DM74LS279 Quad S-R Latches General Description The ’LS279 consists of four individual and independent SetReset Latches with active low inputs Two of the four latches have an additonal S input ANDed with the primary S input A low on any S input while the R input is high will be

Contextual Info: 54LS279,54LS279,DM74LS279 54LS279 54LS279 54LS279 Quad S-R Latches Literature Number: SNOS299A 54LS279 54LS279 DM74LS279 Quad S-R Latches General Description to be indeterminate Both inputs are voltage level triggered and are not affected by transition time of the input data

LS279

Abstract: IC DM74LS279N
Contextual Info: LS279 National JümSemiconductor 54LS279/54LS279/DM74LS279 Quad S-R Latches General Description to be indeterminate. Both inputs are voltage level triggered and are not affected by transition time of the input data. The ’LS279 consists of four individual and independent SetReset Latches with active low inputs. Two of the four latch­

Contextual Info: M MOTOROLA M ilita ry 5 4 LS 2 7 3 O ctal D Flip-Flop With Common Clear M PO E LEC TR IC A LLY TE S T E D PER: M IL-M -38510/32501 The 54LS273 is a high-speed 8-Bit Register. The register consists of eight D type Flip-Flops with a Common C lock and an asynchronous

54LS273/BRB

Contextual Info: M M O T O R O L A M ilita ry 54L S 273 O c tal D Flip-Flop W ith Common C lear ELECTRICALLY TESTED PER: M IL-M -38510/32501 M P O u m n The 54LS273 is a high-speed 8-Bit Register. The register consists of eight D type Flip-Flops with a Common Clock and an asynchronous

54LS27

Abstract: 54LS27DMQB 54LS27FMQB 54LS27LMQB DM54LS27J DM54LS27W DM74LS27M DM74LS27N E20A
Contextual Info: LS27 £ 2 National Semiconductor 54LS27/54LS27/DM74LS27 Triple 3-Input NOR Gates General Description Features This device contains three independent gates each of which performs the logic NOR function. • Alternate Military/Aerospace device 54LS27 is avail­

IC 74279

Abstract: 54LS279A
Contextual Info: SN54279, SN 54LS279 A, S N 74279 , S N 74 LS 2 79 A Q U AD R U PLE S-R LATC HES DECEM BER 1 9 8 3 - Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs S N 54279, SN 54LS279A . . . J OR W PACKAGE

SN74LS27

Abstract: SN7427 kd 617 TTL SN7427 LS27 SN5427 SN54LS27 SN74
Contextual Info: | SN5427, SN 54LS27, SN7427, SN 74LS27 TRIPLE 3 INPUT POSITIVENOR GATES SDLS089 DECEMBER 1 9 8 3 -R E V IS E D M A H C H 1 3 8 8 • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic

Contextual Info: M MOTOROLA Military 54LS27 Triple 3-Input Positive NO R Gate MP0 ELECTRICALLY TESTED PER: MIL-M-38510/30302 mini LOGIC DIAGRAM Vcc C1 Y1 C3 B3 A3 Y3 AVAILABLE AS: 1) JAN: JM38510/30302BXA 2) SMD: N/A 3)883: 54LS27/BXAJC X = CASE OUTLINE AS FOLLOWS: PACKAGE: CERDIP: C

Contextual Info: &> Military 54LS279 MOTOROLA Quad Set-Reset Latch MPO ELECTRICALLY TESTED PER: M IL-M -38510/31602 mini LOGIC DIAGRAM Vq c S4 R4 Q4 S2 AVAILABLE AS: S1 R3 Q3 1 JAN: JM38510/31602BXA 2) SMD: 7601801 3)883: 54LS279/BXAJC X = CASE OUTLINE AS FOLLOWS: PACKAGE: CERDIP: E

ls273

Abstract: 54LS273F
Contextual Info: LS273 a National Semiconductor 54LS273/DM74LS273 8-Bit Register with Clear General Description Features The 'LS273 is a high speed 8-bit register, consisting of eight D-type flip-flops with a common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20pin package featuring 0.3 inch row spacing.

Contextual Info: MOTOROLA M ilitary 54LS279 Quad Set-Reset Latch ELECTRICALLY TESTED PER: MIL-M-38510/31602 AVAILABLE AS: 1 JAN: JM38510/31602BXA 2 ) SMD: 7601801 3» 883C: 54LS279/BXAJC LOGIC DIAGRAM Vcc R4 S4 Q4 3S2 3S1 rïii^imrïïifïïifïïimm X = CASE O UTUNE AS FOLLOWS:

LS27

Contextual Info: LS27 ^ National Semiconductor 54 L S 2 7 /D M 5 4 L S 2 7 /D M 7 4 L S 2 7 Triple 3-lnput NOR Gates General Description Features This device contains three independent gates each of which performs the logic NOR function. • Alternate Military/Aerospace device 54LS27 is avail­

Contextual Info: ^ MOTOROLA M ilitary 54LS273 O ctal D Flip-Flop W ith C o m m o n C le ar ELECTRICALLY TESTED PER: Ml L-M-38510/32501 The 54LS273 is a high-speed 8-Bit Register. The register consists of eight D type Flip-Flops with a Com mon Clock and an asynchronous active LOW Master Reset (CLEAR). This device is supplied in a 20-pin

Contextual Info: M MOTOROLA M ilita ry 54L S 27 Triple 3-In p u t P ositive NOR G a te un mim ELECTRICALLY TESTED PER: MIL-M-38510/30302 LOGIC DIAGRAM V cc Cl Y1 C3 B3 A3 Y3 AVAILABLE AS: 1) JAN: JM38510/30302BXA 2) SMD: N/A 3)883: 54LS27/BXAJC X = CASE OUTLINE AS FOLLOWS:

54LS279

Contextual Info: M Military 54LS279 M O T O R O L A Quad Set-Reset Latch M P O mini ELE CTRICALLY TESTED PER: M IL-M -38510/31602 L O G IC D IA G R A M V cc S4 R4 04 S2 A V A IL A B L E A S : S1 R3 03 R R N R R R N R 1) J A N : J M 3 8 5 1 0/3 1 6 0 2 B X A 2) S M D : 7601801

54LS279DMQB

Abstract: 54LS279FMQB 54LS279LMQB DM54LS279J DM74LS279M DM74LS279N E20A J16A LS279
Contextual Info: & 54LS279/54LS279/DM74LS279 Quad S-R Latches General Description The ’LS279 consists of four individual and independent SetReset Latches with active low inputs. Two of the four latch­ es have an additonal S input ANDed with the primary S input. A low on any S input while the R input is high will be

Contextual Info: M ilita ry 5 4 L S 2 7 9 <8> M OTOROLA Quad S et-R e s et Latch MPO mini ELECTRICALLY TESTED PER: MIL-M-38510/31602 LOGIC DIAGRAM Vcc S4 Q4 R4 S2 AVAILABLE AS: S1 H3 Q3 1 JAN: JM38510/31602BXA 2) SMD: 7601801 3)883: 54LS279/BXAJC X = CASE OUTLINE AS FOLLOWS:

ls273

Abstract: 54LS273F
Contextual Info: LS273 NATIONAL SEMICOND -CLOGIO 31E D L.SD1125 D 0 7 G G 3 4 National Semiconductor T-H é>-& ï- 0 5 54LS273/DM74LS273 8-Bit Register with Clear General Description Features The ’LS273 is a high speed 8-bit register, consisting of eight D-type tiip-flops with a common Clock and an asynchronous

54S273

Abstract: IS1618
Contextual Info: Signetics 54LS273, 54S273 Flip-Flops Octal D Flip-Flops Product Specification Military Logic Products FEATURES DESCRIPTION • Ideal buffer for MOS microprocessor or memory T h e '2 7 3 h a s eight e d g e-trig g ere d D -type ORDERING INFORMATION D ESCRIPTIO N

W14B

Abstract: 54ls27 N14A M14A
Contextual Info: NATIONAL SEMICOND -CLOGIO 31E D • b S Q U S a DGbTTb? 7 ■ National Semiconductor ~T~Ll3 -/6 ~ û û 54LS27/54LS27/DM74LS27 Triple 3-Input NOR Gates General Description Features This device contains three Independent gates each of which performs the logic NOR function.

Contextual Info: NATIONAL SEMICOND {LOGIC* 31E D • bSQUSa National Semiconductor DGbTTb? 7 ■ t -43-/ô- ûô 54LS27/54LS27/DM74LS27 Triple 3-lnput NOR Gates General Description Features This device contains three Independent gates each of which performs the logic NOR function,

54LS273

Abstract: 1N3064
Contextual Info: M M O TO RO LA Military 54LS273 Octal D Flip-Flop With Common Clear ELECTRICALLY TESTED PER: MIL-M-38510/32501 The 5 4L S 2 7 3 is a h igh-speed 8-B it R egister. Th e register consists of e ig h t D typ e Flip-Flops w ith a C om m on C lock and an asynch ro n ou s

IC 74273

Abstract: 74273 IC 74LS273 TTL 74273
Contextual Info: SN54273, SN 54LS273, SN 74 2 73 . SN 74LS 2 73 O C TAL D T Y P E FLIP FLO P WITH CLEAR OCTOBER 1 9 7 6 - REVISED M AR C H 1 9 8 8 S N 5 4 2 7 3 , S N 7 4 L S 2 7 3 . . . J OR W PACKAG E Contains Eight Flip-Flops with Single-Rail Outputs S N 74273. . N PACKAGE