LS279 Search Results

L279

Abstract: 54LS279 LS279
Contextual Info: MICROCIRCUIT DATA SHEET Original Creation Date: 04/13/98 Last Update Date: 07/17/98 Last Major Revision Date: 04/13/98 LS279-X REV 1A0 QUAD SET-RESET LATCH General Description The 'LS279 consists of four individual and independent Set-Reset Latches with active low

LS279

Abstract: IC DM74LS279N
Contextual Info: LS279 National JümSemiconductor LS279/LS279/LS279 Quad S-R Latches General Description to be indeterminate. Both inputs are voltage level triggered and are not affected by transition time of the input data. The ’LS279 consists of four individual and independent SetReset Latches with active low inputs. Two of the four latch­

LS279

Abstract: ls 11m wp-90227-l WP90227l
Contextual Info: LS279 Quad S— R Latch T he LS279 is a bipolar, NPN, sealed-junction, silicon integrated circuit. It is m anufactured in lowpower S ch o ttky te ch no lo g y and is available in a w ire-bonded, 16-pin plastic DIP or surface m ount package. Truth Table Inputs

Contextual Info: LS279 Quad S— R Latch The LS279 is a bipolar, NPN, sealed-junction, silicon integrated circuit. It is manufactured in lowpower Schottky technology and is available in a wire-bonded, 16-pin plastic DIP or surface mount package. 15~| 4S1 ~Ï7| 4R T7| 4Q ~Ï7| 3 S :

Contextual Info: & T fl'ELEC I C 02 D • GGSDDSb 0Q00S4S & ■ '& WA-LS279, WP90227 List 1 Quad S—R Latch The LS279 is a bipolar, NPN, sealed-junction, silicon integrated circuit. It is manufactured in low-power Schottky technology and is available in a wirebonded, 16-pin plastic D IP o r surface m ount package.

LS279

Contextual Info: Quadruple S-R Latches LS279 FEATU R ES • Functionally and Mechanically Identical to 5 4 2 7 9 ■ Features Lo w Power Dissipation o f 19 m W Typical F U N C T IO N T A B L E E A C H L A T C H IN P U T S St OUTPUT R Q H H L H Q0 H H L L L H = h ig h level

WP90227

Abstract: LS279 WA-LS279
Contextual Info: A T & T fl'ELEC I C ÛS D DGSDDSb 0Q0DS4S & « ‘D WA-LS279, WP90227 List 1 Quad S —R Latch The LS279 is a bipolar, NPN, sealed-junction, silicon integrated circuit. It is manufactured in low-power Schottky technology and is available in a wirebonded, 16-pin plastic D IP o r surface m ount package.

Contextual Info: Quadruple S-R Latches LS279 FEATURES • Functionally and Mechanically Identical to 54279 ■ Features Low Power Dissipation of 19 mW Typical F U N C T IO N T A B L E E A C H L A T C H IN P U T S O U TPUT S1 R Q H H L H Q0 H H L L L L H* H = high levef

Contextual Info: LS279 National Semiconductor LS279/LS279/LS279 Quad S-R Latches General Description The ’LS279 consists of four individual and independent Set­ Reset Latches with active low inputs. Two o f the four latch­ es have an additonal 5 input ANDed with the primary §

74HC4096

Abstract: EQUIVALENT TIMER IC WITH CD 4060 rs flip-flop IC 7400 C4050A shiftregister PIPO C148A LS 7476 L1AA C4051A LS294
Contextual Info: Selection Guide C2MOS Logic TC74HC/HCT Series 2. High Speed CMOS Selection Guide GATE NAND HCOOA NOR AND OR INVERTER, BUFFER EXCLUSIVE OR/NOR SC HM ITT TRIGGER HC02A HC08A H C31A H C04A H C86A H C14A H C51A H C4049A M ULTI FUNCTION LEVEL SHIFTER HCTOOA HCT02A

74LS279PC

Abstract: 74279PC 74LS279D 74279 dip 74LS279P 74LS279DC truth table NOT gate 74 54279DM 54279FM 54LS279DM
Contextual Info: 279 C O N N E C T IO N D IA G R A M P IN O U T A / t / 54/74279 11140 !/5 4 L S /7 4 L S 2 7 9 ; ^ / Q U AD SET-RESET LATCH ÏS ] V cc 23 a ¡a m g n d |T O R D E R IN G C O D E : See S e ctio n 9 PIN PK G S OUT C O M M E R C IA L G R A D E M ILIT A R Y G R A D E

LS279

Abstract: 54LS279 54LS279DMQB 54LS279FMQB 54LS279LMQB DM54LS279 DM54LS279J DM74LS279 DM74LS279M DM74LS279N
Contextual Info: LS279 LS279 LS279 Quad S-R Latches General Description The ’LS279 consists of four individual and independent SetReset Latches with active low inputs Two of the four latches have an additonal S input ANDed with the primary S input A low on any S input while the R input is high will be

74LS279N

Abstract: 54LS279W of 74ls279
Contextual Info: S E M IC O N D U C T O R tm LS279 Quad S -R Latches and S inputs from lo w to high will cause the Q output to be in­ determ inate. Both inputs are voltage level triggered and are not affected by transition tim e o f th e input data. General Description

TDA0161 equivalent

Abstract: 1N3393 BDX54F equivalent byt301000 bux transient voltage suppressor ST90R9 ua776mh sgs 2n3055 Transistor morocco mje13007 inmos transputer reference manual
Contextual Info: SHORTFORM 1995 NOVEMBER 1994 USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein:

74LS115

Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
Contextual Info: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25

Contextual Info: SG60R4 Schottky TTL • Over 180 LS Devices • ALS • FAST TOTAL TTL COMMITMENT «TOTAL • TTL Compatible Macrocell Arrays • RAMs • PROMs General Information TTL in Perspective proved speed — p o w e r product co m p ared to LS as a result o f ad vanced M O S A IC oxide isolated processing.

dm8130

Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
Contextual Info: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408

DM74367

Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
Contextual Info: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,

LS279A

Abstract: SN54279 SN54LS279A SN74 SN74279 SN74LS279A
Contextual Info: TYPES SN54279, LS279A, SN74279l LS279A QUADRUPLE S-R LATCHES R E V IS E D D E C E M B E R 1 9 8 3 Package O ptions Include Both Plastic and Ceram ic Chip Carriers in A d dition to Plastic and Ceramic DIPs S N 5427 9, SN 54LS 279A . . . J OR W PACKAGE

IC AND GATE 7408 specification sheet

Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
Contextual Info: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format

sn 74373

Abstract: SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC sn 74377 IC TTL 7486 xor IC TTL 7495 diagram and truth table IC 74374
Contextual Info: PLS-WS/SN MAX+PLUS II Programmable Logic Software for Sun Workstations Data Sheet September 1991, ver. 1 Features J J □ □ □ J □ IJ Softw are supp ort for Classic, M A X 5000, M A X 7000, and S T G EPLD s Runs on Sun S P A R C s ta tio n s with S u n O S version 4.1.1 or h igher

0PIC

Abstract: LS66 SN74L30 84LS 64LS 84ls AX-2016 MAX2719 hy74 L8128A SN7463
Contextual Info: V 84 F A M IL Y S E R IE S 54 S E R IE S M L S S E R IE S B4S S E R IE S 74 S E R IE S 54H S E R IE S 74H S E R IE S 5 4 L 74 F A M IL Y S E R IE S 7 4 L S E R IE S 7 4 LS S E R IE S 74S *00. *04, *H 0 0 ,1404. *L00, 'U M , XSOO, *100, *S04, '10. *20, *30

j6810

Abstract: N74LS279A 54LS279A
Contextual Info: TYPES SN54279, LS279A, SN74279^LS279A QUADRUPLE S R LATCHES R E V IS E D D E C E M B E R 1 9 8 3 Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic DIPs SN5 4 2 7 9 , S N 54LS 279A , . . J OR W PACKAGE

IC 74279

Abstract: 54LS279A
Contextual Info: SN54279, SN LS279 A, S N 74279 , S N 74 LS 2 79 A Q U AD R U PLE S-R LATC HES DECEM BER 1 9 8 3 - Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs S N 54279, SN LS279A . . . J OR W PACKAGE