DM74LS Search Results

74LS241

Abstract: DM74LS240 DM74LS240N DM74LS240SJ DM74LS240WM DM74LS241 DM74LS241N DM74LS241WM M20D
Contextual Info: Revised March 2000 DM74LS240 • DM74LS241 Octal 3-STATE Buffer/Line Driver/Line Receiver General Description Features These buffers/line drivers are designed to improve both the performance and PC board density of 3-STATE buffers/ drivers employed as memory-address drivers, clock drivers, and bus-oriented transmitters/receivers. Featuring

DM74LS243

Abstract: DM74LS243M DM74LS243N M14A MS-001 N14A
Contextual Info: Revised January 2000 DM74LS243 Quadruple Bus Transceiver General Description Features This four data line transceiver is designed for asynchronous two-way communications between data buses. It can be used to drive terminated lines down to 133Ω. • Two-way asynchronous communication between data

DM74LS08N

Abstract: DM74LS08 dm74ls08 quad 2-input and gates DM74LS08M DM74LS08SJ M14A M14D MS-001 N14A
Contextual Info: Revised March 2000 DM74LS08 Quad 2-Input AND Gates General Description This device contains four independent gates each of which performs the logic AND function. Ordering Code: Order Number Package Number Package Description DM74LS08M M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, 0.150 Narrow

DM54LS174

Abstract: 54LS174 54LS174DMQB 54LS174FMQB 54LS175 DM54LS175 DM74LS174 DM74LS175 LS174 LS175
Contextual Info: 54LS174 DM54LS174 DM74LS174 54LS175 DM54LS175 DM74LS175 Hex Quad D Flip-Flops with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad 175 versions feature complementary

74LS90N

Abstract: 74LS93N om504 74ls90 function 74LS93 logic symbol 54LS90 54LS92 DM54LS90 NSB50 CI 74LS90
Contextual Info: DM54LS90/DM74LS90, DM54LS92/DM74LS92, DM54LS93/DM74LS93 Jpg National Jud Semiconductor DM54LS90/DM74LS90, DM54LS92/DM74LS92, DM54LS93/DM74LS93 Decade, Divide by 12, and Binary Counters General Description Features Each o f th e s e m o n o lith ic c o u n te rs c o n ta in s fo u r m a s te r­

Contextual Info: 54LS20,DM54LS20,DM74LS20 54LS20 DM54LS20 DM74LS20 Dual 4-Input NAND Gates Literature Number: SNOS291A 54LS20 DM54LS20 DM74LS20 Dual 4-Input NAND Gates General Description Features This device contains two independent gates each of which performs the logic NAND function

Contextual Info: 54LS30,DM54LS30,DM74LS30 54LS30 DM54LS30 DM74LS30 8-Input NAND Gate Literature Number: SNOS302A 54LS30 DM54LS30 DM74LS30 8-Input NAND Gate General Description Features This device contains a single gate which performs the logic NAND function Y Alternate Military Aerospace device 54LS30 is available Contact a National Semiconductor Sales Office

74LS386N

Abstract: 54LS386 74LS386 DM54 DM74 DM74LS386 54LS386J
Contextual Info: DM54LS386/DM74LS386 National Sim Semiconductor DM54LS386/DM74LS386 Quad 2-Input Exclusive-OR Gates General Description Absolute Maximum Ratings Note 1 This device contains four independent gates each of w hich performs the logic exclusive-OR function. Supply Voltage

54LS368

Abstract: 54LS368A 54LS368ADMQB 54LS368AFMQB 54LS368ALMQB DM54LS368A DM54LS368AJ DM54LS368AW DM74LS368A DM74LS368AM
Contextual Info: 54LS368A DM54LS368A DM74LS368A Hex TRI-STATE Inverting Buffers General Description This device contains six independent gates each of which performs an inverting buffer function The outputs have the TRI-STATE feature When enabled the outputs exhibit the low impedance characteristics of a standard LS output with

LS279

Abstract: 54LS279 54LS279DMQB 54LS279FMQB 54LS279LMQB DM54LS279 DM54LS279J DM74LS279 DM74LS279M DM74LS279N
Contextual Info: 54LS279 DM54LS279 DM74LS279 Quad S-R Latches General Description The ’LS279 consists of four individual and independent SetReset Latches with active low inputs Two of the four latches have an additonal S input ANDed with the primary S input A low on any S input while the R input is high will be

74LS11

Abstract: MK2870-10N05 DM74LS11 DM74LS11M DM74LS11N M14A MS-001 N14A
Contextual Info: Revised March 2000 DM74LS11 Triple 3-Input AND Gate General Description This device contains three independent gates each of which performs the logic AND function. Ordering Code: Order Number Package Number Package Description DM74LS11M M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, 0.150 Narrow

DM74LS86N

Abstract: DM54LS86 DM54LS86J DM54LS86W DM74LS86 DM74LS86M J14A M14A N14A W14B
Contextual Info: DM54LS86 DM74LS86 Quad 2-Input Exclusive-OR Gates General Description This device contains four independent gates each of which performs the logic exclusive-OR function Connection Diagram Dual-In-Line Package TL F 6380 – 1 Order Number DM54LS86J DM54LS86W DM74LS86M or DM74LS86N

74LS151

Abstract: DM74LS151 DM74LS151M DM74LS151N DM74LS151SJ M16A M16D MS-001 N16E
Contextual Info: Revised March 2000 DM74LS151 1-of-8 Line Data Selector/Multiplexer General Description Features This data selector/multiplexer contains full on-chip decoding to select the desired data source. The DM74LS151 selects one-of-eight data sources. The DM74LS151 has a

54LS257A

Abstract: 54LS258A DM54LS257B DM54LS258B DM74LS257B DM74LS258B LS157 LS158
Contextual Info: 54LS257A DM54LS257B DM74LS257B 54LS258A DM54LS258B DM74LS258B TRI-STATE Quad 2-Data Selectors Multiplexers General Description Features These Schottky-clamped high-performance multiplexers feature TRI-STATE outputs that can interface directly with data lines of bus-organized systems With all but one of the

DM74LS503

Abstract: DM74LS503N MS-001 N16E
Contextual Info: Revised March 2000 DM74LS503 8-Bit Successive Approximation Register with Expansion Control General Description Features The DM74LS503 register has an active LOW Enable (E) input that is used in cascading two or more packages for longer word lengths. A HIGH signal on E, after a START

dm74ls174n

Contextual Info: Revised April 2000 DM74LS174 • DM74LS175 Hex/Quad D-Type Flip-Flops with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad 175 versions feature complementary

multiplexer

Abstract: multiplexer 2to1 selector transistors bipolar DM74150 DM74157 DM74ALS151 DM74ALS153 multiplexer/14052B DM74AS157
Contextual Info: Logic Products by Function Selector Products Logic Product Family Product Description Package Voltage Node DM74150 Bipolar-TTL Data Selector/Multiplexer DIP 5 DM74ALS151 Bipolar-ALS 1 of 8 Line Data Selector/Multiplexer DIP SOIC 5 DM74LS151 Bipolar-LS 1-of-8 Line Data Selector/Multiplexer

master slave jk flip flop

Abstract: ECL D flip flop Flip Flop DIP Flip flop JK cmos 74lvt16374 d flip flop d type flip flop flip flop flip flop circuit flip flop circuit type D
Contextual Info: Logic Products by Function Flip-Flop Products Logic Product Family Product Description Package Voltage Node 74ACT109 FACT ACT Dual JK Positive Edge-Triggered Flip-Flop DIP SOIC TSSOP 5 DM74LS73A Bipolar-LS Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary

26series

Abstract: hex to 7 segment decoder line driver 74ABT240 74AC240 74AC540 74ACQ240 74ACT1284 DM74145 DM74LS47
Contextual Info: Logic Products by Function Line Driver Products Logic Product Family Product Description Package Voltage Node MM88C29 74C CMOS Quad Single-Ended Line Driver DIP 5 other MM88C30 74C CMOS Dual Differential Line Driver DIP SOIC 5 other DM74LS47 Bipolar-LS BCD to 7-Segment Decoder/Driver

Contextual Info: S E M IC O N D U C T O R tm DM74LS138, DM74LS139 Decoders/Demultiplexers General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applica­ tions, requiring very short propagation delay times. In

74LS283N

Contextual Info: S E M IC O N D U C T O R tm DM74LS283 4-Bit Binary Adders with Fast Carry • System s achieve partial look-ahead perform ance with the econom y of ripple carry General Description These full adders perform the addition o f tw o 4-bit binary num bers. The sum E outputs are provided for each bit and

Contextual Info: R C H U - P S E M IC O N D U C T O R tm DM74LS47 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs General Description Features The ’LS47 accepts fo u r lines of BC D 8421 input data, gen­ erates th e ir com plem ents internally and decodes the data

Contextual Info: May 1992 DM54LS447/DM74LS447 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs General Description The ’LS447 is the same as the ’LS247 except that the Out­ put OFF Voltage, Vqh is specified as 7.0 V rather than 15V, with the same Ioh limit of 250

dm74ls377n

Abstract: DM74LS377 DM54LS377 DM54LS377E DM54LS377J DM54LS377W DM74LS377WM E20A J20A LS377
Contextual Info: DM54LS377 DM74LS377 Octal D Flip-Flop with Common Enable and Clock General Description Features The ’LS377 is an 8-bit register built using advanced low power Schottky technology This register consists of eight D-type flip-flops with a buffered common clock and a buffered common input enable The device is packaged in the