512K Search Results

Contextual Info: o bq4850Y U N I T R O D E - RTC Module with 512Kx8 NVSRAM Features General Description >• I n te g r a t e d SRAM, re a l-tim e clock, crystal, power-fail control circuit, and battery The bq4850Y RTC Module is a non­ volatile 4,194,304-bit SRAM organ­

character generater

Contextual Info: 4M BIT 256K W O RD x 16 B IT / 512K W O R D x 8BIT CM OS M ASK ROM DESCRIPTION The BYTE The The TC534200P/F is a 4,194,304 bits read only memory organized as 262,144 words by 16 bits when is logical high, and is organized as 524,288 words by 8 bits when BYTE is logical low.

Contextual Info: TMS28F040 4 194 304-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY SMJS040-DECEMBER 1992 N PACKAGET Organization . . . 512K x 8 Separately Erasable 32K Byte Blocks Two Power Supplies 5 V and 12 V 100% TTL-Level Control Inputs Fully Automated On-Chip Erase and Byte

A18D0

Abstract: TC534000AP
Contextual Info: Slsllllf I I I ! llllll ¡11 4M BIT 512K W O R D x 8 B IT CMOS MASK ROM DESCRIPTION The TC534000AP/AF is a 4,194,304 bits read only memory organized as 524,288words by 8bits. The TC534000AP / AF is fabricated using Toshiba’s advanced CMOS technology which provides the

Contextual Info: SMJ684002 512K BY 84HT STATIC RANDOM-ACCESS MEMORY _ * Single 5-V ± 10% Power Supply HJA/HKE PACKAGE TOP ViEW f • • Fast Access Time 20125/35 ns Equal Address and Chip-Enable Access Time • • • All Inputs and Outputs Are TTL-Compatible

Contextual Info: S M J27C 040 4 1 9 4 3 0 4 -B IT U V E R A S A B LE P R O G R A M M A B L E R E A D -O N L Y M E M O R Y SGMS046A-NOVEMBER 1992- REVISEDJUNE 1995 • Organization . . . 512K x 8 Jpackage • Single 5-V Power Supply T0P V1EW • Industry Standard 32-Pin Dual-ln-llne

23A512-I

Abstract: 23A512 23LC512-I 23LC512
Contextual Info: 23A512/23LC512 512Kbit SPI Serial SRAM with SDI and SQI Interface Device Selection Table Part Number VCC Range Dual I/O SDI Quad I/O (SQI) Max. Clock Frequency 23A512 1.7-2.2V Yes Yes 20 MHz SN, ST, P 23LC512 2.5-5.5V Yes Yes 20 MHz SN, ST, P Packages Features:

IS42VS16100E

Abstract: 42VS16100E IS42VS16100E-75BLI
Contextual Info: IS42VS16100E 512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 133, 100, 83 MHz • Fully synchronous; all signals referenced to a positive clock edge • Two banks can be operated simultaneously and independently • Dual internal bank controlled by A11

Contextual Info: SRAM 512K8 Austin Semiconductor, Inc. 512K x 8 SRAM PIN ASSIGNMENT Top View HIGH SPEED SRAM with REVOLUTIONARY PINOUT 36-Pin SOJ (DJ & ECJ) 36-Pin CLCC (EC) AVAILABLE AS MILITARY SPECIFICATIONS •SMD 5962-95600 •MIL-STD-883 FEATURES • Ultra High Speed Asynchronous Operation

Contextual Info: SRAM AS5C4008 Austin Semiconductor, Inc. 512K x 8 SRAM PIN ASSIGNMENT Top View SRAM MEMORY ARRAY AVAILABLE AS MILITARY SPECIFICATION 32-Pin DIP (CW), 32-Pin LCC (EC) 32-Pin SOJ (ECJ) • SMD 5962-95600 • MIL STD-883 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1

Contextual Info: M27W401 4 Mbit 512Kb x 8 Low Voltage UV EPROM and OTP EPROM Features • 2.7V to 3.6V Supply Voltage in Read Operation ■ Access Time: – 70 ns at VCC = 3.0V to 3.6V – 80 ns at VCC = 2.7V to 3.6V ■ ■ Pin Compatible with M27C4001 1 Programming Time 100 µs/byte

fm25v05-g

Abstract: FM25V05 fm25v05g
Contextual Info: FM25V05 512Kb Serial 3V F-RAM Memory Features 512K bit Ferroelectric Nonvolatile RAM • Organized as 65,536 x 8 bits  High Endurance 100 Trillion 1014 Read/Writes  10 Year Data Retention  NoDelay Writes  Advanced High-Reliability Ferroelectric Process

Contextual Info: SDRAM AS4SD2M32 512K x 32 x 4 Banks 64-Mb PIN ASSIGNMENT (Top View) Synchronous SDRAM 86-Pin TSOPII FEATURES • Full Military temp (-55°C to 125°C) processing available • Configuration: 512K x 32 x 4 banks • Fully synchronous; all signals registered on positive

Contextual Info: SRAM 512K32 & 512K32A 512K x 32 SRAM PIN ASSIGNMENT Top View SRAM MEMORY ARRAY AVAILABLE AS MILITARY SPECIFICATIONS NC A0 A1 A2 A3 A4 A5 CS3\ GND CS4\ WE1\ A6 A7 A8 A9 A10 Vcc 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 SMD 5962-94611 (Military Pinout)

K4S643233H

Abstract: K4S643233H-F
Contextual Info: K4S643233H - F H E/N/G/C/L/F Mobile-SDRAM 512K x 32Bit x 4 Banks Mobile SDRAM in 90FBGA FEATURES GENERAL DESCRIPTION • 3.0V & 3.3V power supply. The K4S643233H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,

MS-026

Abstract: MT55L256L32P MT55L256L36P MT55L256V32P MT55L256V36P MT55L512L18P MT55L512V18P
Contextual Info: 8Mb: 512K x 18, 256K x 32/36 PIPELINED ZBT SRAM 8Mb ZBT SRAM MT55L512L18P, MT55L512V18P, MT55L256L32P, MT55L256V32P, MT55L256L36P, MT55L256V36P 3.3V VDD, 3.3V or 2.5V I/O FEATURES • • • • • • • • • • • • • • • • • • •

16mb HIGH-SPEED ASYNCHRONOUS SRAM

Abstract: IBM041816CHLBC IBM043616CHLBC SA37T
Contextual Info: . IBM043616CHLBC IBM041816CHLBC 16Mb 512K x 36 & 1M x 18 SRAM Features • 512K x 36 or 1M x 18 organization • Registered addresses, controls, and data-ins • CMOS technology • Burst mode of operation • Double-data-rate and single-data-rate synchronous mode of operation

SA37T

Abstract: cq 721 IBM041816CBLBC IBM043616CBLBC
Contextual Info: . IBM043616CBLBC IBM041816CBLBC 16Mb 512K x 36 & 1M x 18 SRAM Features • 512K x 36 or 1M x 18 organization • Registered addresses, controls, and data-ins • CMOS technology • Burst mode of operation • Double-data-rate and single-data-rate synchronous mode of operation

a29040al-70

Abstract: A29040A-55 A29040A A29040A-70 A29040AL A29040AL-55 A29040AV-55 IN3064
Contextual Info: A29040A Series 512K X 8 Bit CMOS 5.0 Volt-only, Preliminary Uniform Sector Flash Memory Features n 5.0V ± 10% for read and write operations n Access times: - 55/70/90 max. n Current: - 20 mA typical active read current - 30 mA typical program/erase current

K7Q161852A

Abstract: K7Q161852A-FC10 K7Q161852A-FC13 K7Q161852A-FC16 K7Q163652A K7Q163652A-FC10 K7Q163652A-FC13 K7Q163652A-FC16
Contextual Info: K7Q163652A K7Q161852A 512Kx36 & 1Mx18 QDRTM b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit QDRTM SRAM Revision History History Draft Date Remark 0.0 1. Initial document. April, 30, 2001 Advance 0.1 1. Amendment 1 Page 3,4 PIN NAME DESCRIPTION W 4A) : from Read Control Pin to Write Control

K7Z327285M

Contextual Info: K7Z327285M Preliminary 512Kx72 DLW Double Late Write RAM Document Title 512Kx72 DLW(Double Late Write) RAM Revision History Rev. No. 0.0 0.1 History Draft Date Remark 1. Initial document. 1. Device name change from Double Late Write SigmaRAM to Double Late Write RAM

MT48LC2M32B2P

Abstract: MT48LC2M32B2 MT48LC2M32B2P-7 MT48LC2M32B2TG 2M32B2 *48LC2M32 H9612
Contextual Info: 64Mb: x32 SDRAM Features Synchronous DRAM MT48LC2M32B2 – 512K x 32 x 4 banks For the latest data sheet, refer to Micron’s Web site Features Table 1: • PC100 functionality • Fully synchronous; all signals registered on positive edge of system clock

IBM0418A41NLAB

Abstract: IBM0418A81NLAB IBM0436A41NLAB IBM0436A81NLAB
Contextual Info: IBM0436A41NLAB IBM0418A41NLAB IBM0418A81NLAB IBM0436A81NLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM . Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • Registered outputs • 30 Ω drivers

IS61WV51232BLL-10BLI

Abstract: IS61WV51232BLL IS64WV51232BLL IS61WV51232 IS64WV51232BLL-10BA3
Contextual Info: IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS 512K x 32 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY FEATURES • High-speed access times: 8, 10, 20 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater