11X19 Search Results

Contextual Info: MEMORY MODULE DDR2 SDRam 128Mx72-BGA 3D2D8G72UB3369 DDR2 Synchronous Dynamic Ram 8Gbit DDR2 SDRam organized as 128Mx72, based on 128Mx16 MODULE Pin Assignment Top View BGA 208 - (11x19 - Pitch 1.00mm) (TOP VIEW - VIEWED BY TRANSPARENCY) 11 10 9 8 7 6 5 4

Contextual Info: MEMORY MODULE DDR2 SDRam 64Mx72-BGA 3D2D4G72UB3416 DDR2 Synchronous Dynamic Ram 4Gbit DDR2 SDRam organized as 64Mx72, based on 64Mx16 MODULE Pin Assignment Top View BGA 208 - (11x19 - Pitch 1.00mm) (TOP VIEW - VIEWED BY TRANSPARENCY) 11 10 9 8 7 6 5 4 3

K7Z327285M

Contextual Info: K7Z327285M Preliminary 512Kx72 DLW Double Late Write RAM Document Title 512Kx72 DLW(Double Late Write) RAM Revision History Rev. No. 0.0 0.1 History Draft Date Remark 1. Initial document. 1. Device name change from Double Late Write SigmaRAM to Double Late Write RAM

K7N327245M

Abstract: K7N327249M
Contextual Info: Preliminary 512Kx72 Pipelined NtRAMTM K7N327245M Document Title 512Kx72-Bit Pipelined NtRAM TM Revision History Rev. No. 0.0 0.1 History Draft Date Remark 1. Initial document. 1. Speed bin merge. From K7N327249M to K7N327245M 2. AC parameter change. tOH min /tLZC(min) from 0.8 to 1.5 at -25

CXK79M36C163GB

Abstract: CXK79M36C163GB-33 CXK79M36C163GB-4 CXK79M36C163GB-5
Contextual Info: SONY ΣRAM CXK79M36C163GB 18Mb 1x2Lp LVCMOS High Speed Synchronous SRAMs 512Kb x 36 33/4/5 Preliminary Description The CXK79M36C163GB is a high speed CMOS synchronous static RAM with common I/O pins. It is manufactured in compliance with the JEDEC-standard 209 pin BGA package pinout defined for SigmaRAM™ devices. It integrates input registers,

256Kx72

Abstract: EP-3 ae2a
Contextual Info: Preliminary 256Kx72 Double Late Write SigmaRAMTM K7N167285A 256Kx72-Bit Pipelined SigmaRAMTM FEATURES GENERAL DESCRIPTION • Double Late Write mode , Pipelined Read mode. • 1.8V+150/-100 mV Power Supply. • 1.8V I/O supply. • Byte Writable Function.

CXK79M36C160GB

Abstract: CXK79M36C160GB-33 CXK79M36C160GB-4 CXK79M36C160GB-5 CXK79M72C160GB CXK79M72C160GB-33 CXK79M72C160GB-4 CXK79M72C160GB-5
Contextual Info: SONY ΣRAM CXK79M72C160GB / CXK79M36C160GB 18Mb 1x1Lp HSTL High Speed Synchronous SRAMs 256Kb x 72 or 512Kb x 36 33/4/5 Preliminary Description The CXK79M72C160GB (organized as 262,144 words by 72 bits) and the CXK79M36C160GB (organized as 524,288 words

M5M5T5672TG-20

Abstract: a01-824
Contextual Info: Renesas LSIs M5M5T5672TG – 20 Preliminary Notice: This is not final specification. Some parametric limits are subject to change. 18874368-BIT 262144-WORD BY 72-BIT NETWORK SRAM DESCRIPTION The M5M5T5672TG is a family of 18M bit synchronous SRAMs organized as 262144-words by 72-bit. It is designed to eliminate

CXK79M72C164GB-33

Abstract: CXK79M18C164GB CXK79M36C164GB CXK79M36C164GB-33 CXK79M36C164GB-4 CXK79M72C164GB CXK79M72C164GB-4 CXK79M72C164GB-5
Contextual Info: SONY ΣRAM CXK79M72C164GB CXK79M36C164GB CXK79M18C164GB 18Mb 1x1Dp HSTL High Speed Synchronous SRAMs 256Kb x 72 or 512Kb x 36 or 1Mb x 18 33/4/5 Preliminary Description The CXK79M72C164GB (organized as 262,144 words by 72 bits), CXK79M36C164GB (organized as 524,288 words by 36

Contextual Info: IS61LSCS25672 IS61LSCS51236 ISSI SRAM 256K X 72, 512K X 36 ADVANCE INFORMATION JUNE 2002 18MB SYNCHRONOUS SRAM FEATURES • JEDEC SigmaRam pinout and package standard • Single 1.8V power supply VCC : 1.7V (min) to 1.9V (max) • Dedicated output supply voltage (VCCQ): 1.8V

Contextual Info: SONY ΣRAM CXK79M72C165GB CXK79M36C165GB CXK79M18C165GB ΣRAMs: 16Mb 1x1z LVCMOS I/O 256K x 72 or 512K x 36 or 1M x 18 Organization 33/4/44 Preliminary Description The CXK79M72C165GB (organized as 262,144 words by 72 bits), CXK79M36C165GB (organized as 524,288 words by 36

Contextual Info: Preliminary 512Kx72 Pipelined NtRAM TM K7N327245M Document Title 512Kx72-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 0.1 1. Initial document. 1. Speed bin merge. From K7N327249M to K7N327245M 2. AC parameter change. tOH min /tLZC(min) from 0.8 to 1.5 at -25

tc-l 11w

Abstract: K7N167245A K7N167249A
Contextual Info: Preliminary 256Kx72 Pipelined NtRAMTM K7N167245A Document Title 256Kx72-Bit Pipelined NtRAM TM Revision History Rev. No. 0.0 0.1 0.2 0.3 History Draft Date Remark 1. Initial document. 1. Add JTAG Scan Order 1. Upate DC characteristics icc,isb 1. Speed bin merge.

bwh series

Abstract: ECHO schematic diagrams
Contextual Info: MITSUBISHI LSIs 2001.May Rev.0.1 M5M5Y5672TG – 25,22,20 Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. 18874368-BIT 262144-WORD BY 72-BIT NETWORK SRAM DESCRIPTION The M5M5Y5672TG is a family of 18M bit synchronous SRAMs

CC2500

Contextual Info: Anaren Integrated Radio AIR Low-power R F modules, firmware & development tools that make it easy to ’go wireless’ BoosterPack Series The A2541R24A-ADB1 B-SMART BoosterPack kit is a development tool designed for use with the TI MSP430TM Value Line, TiVA-C, C2000 and other LaunchPad kits. The kit eases

CCATS

Contextual Info: Anaren Integrated Radio AIR Low-power RF modules, firmware & development tools that make it easy to ’go wireless’ BoosterPack Series The A2530E24A-LPZ is an AIR Module BoosterPack kit for the MSP430TM Value Line or Tiva C LaunchPad Development Kit. This kit eases the development of products

Contextual Info: Anaren Integrated Radio AIR Low-power RF modules, firmware & development tools that make it easy to ’go wireless’ 2541 System on Chip Series The A2541R24C is a surface-mount radio module featuring Bluetooth SMART technology that incorporates the Texas Instruments ultra-low-power CC2541 SoC,

306FSR300XZ2BW

Contextual Info: FEATURES Reduced case size - High voltage – Low Leakage – low dissipation Factor – JIS 2365 Compliant APPLICATIONS Emergency lights – Signal lights Operating Temperature Range Capacitance Tolerance WVDC Surge voltage SVDC Dissipation Factor tan δ

BGA676

Abstract: BGA665 BGA-1156 156 QFN 12X12 LGA240 BGA-783 BGA441 BGA1024 BGA1521 7286X
Contextual Info: Ironwood Electronics Appendix A AP-A.1 APPENDIX A • BGA Chip Package Specification Tables . . . . . . . .page AP.2 thru AP.16 • LGA Chip Package Specification Table . . . . . . . . . . . . . . . . .page AP.17 • MLF Package Specification Table . . . . . . . . . . . . . . . . . . . . .page AP.18

CXK79M18C160GB

Abstract: CXK79M36C160GB CXK79M36C160GB-33 CXK79M72C160GB CXK79M72C160GB-33 CXK79M72C160GB-4
Contextual Info: SONY ΣRAM CXK79M72C160GB CXK79M36C160GB CXK79M18C160GB 16Mb 1x1Lp HSTL High Speed Synchronous SRAMs 256Kb x 72 or 512Kb x 36 or 1Mb x 18 33/4/44 Preliminary Description The CXK79M72C160GB (organized as 262,144 words by 72 bits), CXK79M36C160GB (organized as 524,288 words by 36

CXK79M18C163GB

Abstract: CXK79M18C163GB-33 CXK79M18C163GB-4 CXK79M36C163GB CXK79M36C163GB-33 CXK79M36C163GB-4
Contextual Info: SONY ΣRAM CXK79M36C163GB / CXK79M18C163GB 16Mb 1x2Lp LVCMOS High Speed Synchronous SRAMs 512Kb x 36 or 1Mb x 18 33/4/44 Preliminary Description The CXK79M36C163GB (organized as 524,288 words by 36 bits) and the CXK79M18C163GB (organized as 1,048,576 words

a7w29

Abstract: CXK79M36C163GB-33 CXK79M36C163GB-4 CXK79M36C163GB-5 CXK79M18C163GB CXK79M18C163GB-33 CXK79M18C163GB-4 CXK79M18C163GB-5 CXK79M36C163GB
Contextual Info: SONY ΣRAM CXK79M36C163GB / CXK79M18C163GB 18Mb 1x2Lp LVCMOS High Speed Synchronous SRAMs 512Kb x 36 or 1Mb x 18 33/4/5 Preliminary Description The CXK79M36C163GB (organized as 524,288 words by 36 bits) and the CXK79M18C163GB (organized as 1,048,576 words

Contextual Info: MITSUBISHI LSIs September 3, 2002 Rev.0.7 M5M5Y5672TG – 25,22,20 Preliminary Notice: This is not final specification. Some parametric limits are subject to change. 18874368-BIT 262144-WORD BY 72-BIT NETWORK SRAM DESCRIPTION FUNCTION The M5M5Y5672TG is a family of 18M bit synchronous SRAMs

Contextual Info: MITSUBISHI LSIs 2002. July Rev.0.4 M5M5Y5636TG – 25,22,20 Preliminary Notice: This is not final specification. Some parametric limits are subject to change. 18874368-BIT 524288-WORD BY 36-BIT NETWORK SRAM DESCRIPTION FUNCTION The M5M5Y5636TG is a family of 18M bit synchronous SRAMs