512KX72 Search Results

NtRAM

Abstract: K7N327245M K7N327249M
Contextual Info: Preliminary 512Kx72 Pipelined NtRAM TM K7N327245M Document Title 512Kx72-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 1. Initial document. May. 10. 2001 Advance 0.1 1. Speed bin merge. From K7N327249M to K7N327245M 2. AC parameter change.

W2Z512K72SJ

Contextual Info: W2Z512K72SJ 36Mb, 512Kx72 Synchronous Pipeline Burst NBL SRAM Preliminary* FEATURES DESCRIPTION n Fast clock speed: 225, 200, 166 and 150MHz The WEDC SyncBurst - SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 72Mb

K7N321801M

Abstract: K7N323601M
Contextual Info: K7N323601M K7N321801M Preliminary 1Mx36 & 2Mx18 Pipelined NtRAMTM Document Title 1Mx36 & 2Mx18-Bit Pipelined NtRAMTM Revision History Rev. No. 0.0 0.1 0.2 Draft Date History 1. Initial document. 1. Add 165FBGA package 1. Update JTAG scan order 2. Speed bin merge.

Contextual Info: K7N323601M K7N321801M 1Mx36 & 2Mx18 Pipelined NtRAM TM Document Title 1Mx36 & 2Mx18-Bit Pipelined NtRAM TM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. May. 10. 2001 Preliminary 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary

9261A

Abstract: UFO 128
Contextual Info: fax id: 2042 CYM9260 CYM9261A/B CYM9262A/B CYM9263 64Kx 72 SRAM 128K x 72 SRAM 256K x 72 SRAM 512K x 72 SRAM Featu res • Operates at 50 MHz • Uses 6 4 K x 1 8 /1 2 8 K x 1 8 o r2 5 6 K x 18 high performance synchronous SRAMs • 168-position Angled DIMM from Amp p/n 179508-2

9262a

Abstract: 72nC
Contextual Info: CYM9260 CYM9261B CYM9262A CYM9263 62A 64K x 72 SRAM Module 128K x 72 SRAM Module 256K x 72 SRAM Module 512K x 72 SRAM Module Features • Operates at 66 MHz • Uses 64K x 18, 128K x 18, or 256K x 18 high performance synchronous SRAMs • 168-position Angled DIMM from Amp p/n 179508-2

CY7C1461V33

Abstract: CY7C1463V33
Contextual Info: CY7C1461V33 CY7C1463V33 CY7C1465V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles •Supports 133-MHz bus operations •1M x 36/2M × 18/512K × 72 common I/O

Contextual Info: CY7C1447V25 CY7C1443V25 CY7C1441V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-Thru SRAM Features inputs are gated by registers controlled by a positiveedge-triggered clock input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip

W986416EH

Abstract: W9864G2EH W981216DH verilog DTMF decoder ISD1600 W9825G6CH W9812G6DH w981616ch SIS 730S isd1620
Contextual Info: PRODUCT GUIDE Winbond ISSI 2005 http://www.hengsen.cn 产品指南手册 PRODUCT GUIDE =WinbondISSI 授权香港及中国代理= 8 位单片机标准件 型号 W78C32C ROM 型式 ROM ROM RAM I/O 脚 外扩存储 器空间 工作速度 封装 定时器/

CY7C1460V33

Abstract: CY7C1462V33
Contextual Info: CY7C1460V33 CY7C1462V33 CY7C1464V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 250, 200, and 167 MHz • Fast access time: 2.7, 3.0 and 3.5 ns

CY7C1461V25

Abstract: CY7C1463V25 CY7C1465V25
Contextual Info: CY7C1461V25 CY7C1463V25 CY7C1465V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 F/T SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles •Supports 133-MHz bus operations •1M x 36/2M x18/512K x 72 common I/O

CY7C1441V33

Abstract: CY7C1443V33
Contextual Info: CY7C1441V33 CY7C1443V33 CY7C1447V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-through SRAM Features •Supports 133–MHz bus operations •1M x 36/2M x 18/512K x 72 common I/O •Fast clock–to–output times — 6.5 ns for 133–MHz device — 7.5 ns (for 117–MHz device)

VIPER 17H

Abstract: VIPER 27h 82c568 82C621A 486 system bus Viper 15 82C576 82C578 bios programmer 1F3H
Contextual Info: OPTi Inc. OPTi 888 Tasman Drive Milpitas, CA 95035 408 486-8000 Fax: (408) 486-8001 Application Note (OPTi Confidential) Product Name: Viper Xpress+ Chipset Title: BIOS Programming Guide Date: January 16, 1997 Scope Discussion This document outlines the recommended procedure for programming the internal registers of the Viper Xpress+ Chipset.

TMS 1070 NL

Abstract: CYD09S18V18-167BBXC CYD09S36V18 CYD18S36V18 CYD04S18V18-200BBXC FullFlex36
Contextual Info: FullFlex FullFlex Synchronous SDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with Single Data Rate SDR operation on each port — SDR interface at 250 MHz

FullFlex36

Contextual Info: PRELIMINARY FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port

CYD04S18V18-200BBXC

Abstract: A20l cqe vco CYD18S36V18-200BBXI TMS 1070 NL FullFlex36
Contextual Info: FullFlex FullFlex Synchronous SDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with Single Data Rate SDR operation on each port — SDR interface at 250 MHz

Contextual Info: K7N323601M K7N321801M Preliminary 1Mx36 & 2Mx18 Pipelined NtRAM TM Document Title 1Mx36 & 2Mx18-Bit Pipelined NtRAMTM Revision History Rev. No. 0.0 Draft Date History May. 10. 2001 1. Initial document. Remark Preliminary The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

K7N321801M

Abstract: K7N323601M
Contextual Info: K7N323601M K7N321801M Preliminary 1Mx36 & 2Mx18 Pipelined NtRAMTM Document Title 1Mx36 & 2Mx18-Bit Pipelined NtRAMTM Revision History Rev. No. 0.0 0.1 0.2 0.3 0.4 Draft Date History 1. Initial document. 1. Add 165FBGA package 1. Update JTAG scan order 2. Speed bin merge.

K7N321845M

Abstract: K7N323645M
Contextual Info: K7N323645M K7N321845M Preliminary 1Mx36 & 2Mx18 Pipelined NtRAMTM Document Title 1Mx36 & 2Mx18-Bit Pipelined NtRAMTM Revision History Rev. No. 0.0 0.1 0.2 0.3 0.4 0.5 History Draft Date Remark 1. Initial document. 1. Add 165FBGA package 1.Update JTAG scan order