4B2L Search Results

Contextual Info: Ä M Ä K I I 0 M F @ [^ O ii]Ä ¥ 0 ® M VS28F016XS, MS28F016XS 16-MBIT 1 MBIT x 16, 2 MBIT x 8 SYNCHRONOUS FLASH MEMORY • VS28F016XS 40°C to +125°C — QML Certified — SE2 Grade ■ 0.25 MB/sec Write Transfer Rate ■ MS28F016XS 55°C to 125°C

Contextual Info: in t e P R S y f flO O K I M tf i 8 0 C 19 8 /8 3 C 19 8 /8 0 C 19 4 /8 3 C 1 9 4 COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER 83C198 — 8 Kbytes of Factory Mask-Programmed ROM 80C198 — ROMIess 232 Byte Register File Full Duplex Serial Port Register-to-Register Architecture

intel i386 ex circuit diagram

Abstract: intel 80368 Instruction set Architecture i386 ex board M82384 i386 dx ICE-386 271052 271062 i386 SL M8088
Contextual Info: SñE J> • intei 462bl75 D I S H E D 17T ¡ITL1 INTEL CORP ÜP/PRPHLS ' T ' L t cv - n - y t - f MILITARY ¡386 HIGH PERFORMANCE 32-BIT MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT Flexible 32-Bit Microprocessor — 8, 16, 32-Bit Data Types — 8 General Purpose 32-Bit Registers

80186xl

Abstract: ARCHITECTURE OF 80186 PROCESSOR 8086 opcode sheet DAA INstruction 80166 intel 80186 instruction set intel 80186 pin out 80186 architecture intel 80188 80188 internal control block intel 80186 external memory
Contextual Info: inUI 80186/80188 HIGH-INTEGRATION 16-BIT MICROPROCESSORS • Integrated Feature Set — Enhanced 8086-2 CPU — Clock Generator — 2 Independent DMA Channels — Programmable Interrupt Controller — 3 Programmable 16-bit Timers — Programmable Mem ory and

compal service manual

Abstract: M/1E54H 1E06H
Contextual Info: in tel. APPENDIX C REGISTERS This appendix provides reference information about the device registers. Table C-l lists the mod­ ules and major components of the device with their related configuration and status registers. Ta­ ble C-2 lists the registers, arranged alphabetically by mnemonic, along with their names,

gi 9644 diode

Abstract: INTELDX4 write-through
Contextual Info: in te i, MILITARY Intel 486 PROCESSOR FAMILY • Write-Back Enhanced ln t e l D X 4 ™ Processor — Up to 100-MHz Operation -Speed-M ultiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Write-Back Cache — Integrated Floating-Point Unit

diodo sl r7

Abstract: TMs 1122 NL BC 1305 pin outs DIODO 6N c11 cpl 100 39p HBT 01 - 04G Intel486TM PROCESSOR FAMILY 6M91 INTEL I486 DX2 diodo s4 6n
Contextual Info: intei MILITARY ln t e l 486 TM PROCESSOR FAMILY • lntelDX4TM Processor — Up to 100-MHz Operation -S peed-M ultiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Cache — Integrated Floating-Point Unit — 3.3V Core Operation with 5V Tolerant

ma6351

Abstract: LE-24T ZO 607MA A82496 290446 EM 5135 diode 522110 jp 486TM 241429 dm4021
Contextual Info: INTEL CORP -CUP/PRPHLSJ S7E D • 4 fl2 bl 7 5 01522147 t»23 ■ in te l Pentium Processor User's Manual Volume 2: 82496 Cache Controller and 82491 Cache SRAM Data Book NOTE: The Pentium™ Processor User's Manual consists of three books: Pentium™ Processor Data Book, Order Number 241428; the

Contextual Info: 80960H A/H D/HT in te i 1.0 ABOUT THIS DOCUMENT This document describes the parametric perfor­ mance of Intel’s 80960Hx embedded superscalar microprocessors. Detailed descriptions for functional topics — other than parametric performance — are published in the i9 6 P H x M icroprocessor User’s

5a6h

Contextual Info: intel CHAPTER 6 INSTRUCTION SET REFERENCE This chapter provides detailed information about each instruction available to the i960 Rx I/O processor. Instructions are listed alphabetically by assembly language mnemonic. Format and notation used in this chapter are defined in section 6.1 . NOTATION pg. 61 .

82420EX

Contextual Info: in te i 82420EX PCISET DATA SHEET 82425EX PCI SYSTEM CONTROLLER PSC AND 82426EX ISA BRIDGE (IB) Host CPU - 2 5 - 3 3 MHz ln te l4 8 6 T M and Programmable Attribute Map for First 1 MByte of Main Memory O v e rD riv e P ro ce ss o rs 100% ISA Compatible

01ag

Abstract: ML616
Contextual Info: in te l CHAPTER 3 INSTRUCTION SET REFERENCE This chapter describes the complete Intel Architecture instruction set, including the integer, floating-point, MMX technology, and system instructions. The instruction descriptions are arranged in alphabetical order. For each instruction, the forms are given for each operand combi­

Contextual Info: Intel 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Dem ultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two Instructions/clock Execution

Contextual Info: A28F010 1024K 128K x 8 CMOS FLASH MEMORY (Autom otive) • Automotive Temperature Range: —40°C to + 1 25°C ■ Flash Memory Electrical Chip-Erase — 1 Second Typical Chip-Erase ■ Quick-Pulse Programming Algorithm — 10 jas Typical Byte-Program — 2 Second Chip-Program

AN87C196KT

Abstract: 87C196KT
Contextual Info: in té l 87C196KT/87C196KS 20 MHz ADVANCED 16-BIT CHMOS MICROCONTROLLER A u to m o tiv e —40°C to + 125°C Ambient High Performance CHMOS 16-Bit CPU Up to 32 Kbytes of On-Chip EPROM High Speed Peripheral Transaction Server (PTS) Up to 1 Kbyte of On-Chip Register RAM

XK power 22E

Abstract: slb 9635 tt 1.2 SLB 9635 TMs 1122 NL CU 212 SLB 9635 TT INTELDX4 write-through intel DX4 WHAT IS 485 PROTOCOL Intel486
Contextual Info: intei MILITARY l n t e l 486 TM PROCESSOR FAMILY • lntelDX4TM Processor — Up to 100-MHz Operation — Speed-Multiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Cache — Integrated Floating-Point Unit — 3.3V Core Operation with 5V Tolerant

Contextual Info: intgl 8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER High Performance CHMOS 16-bit CPU 16 MHz Operating Frequency 32 Kbytes of On-chip OTPROM/ROM 744 Bytes of On-chip Register RAM Register-to-register Architecture 16 Prioritized Interrupt Sources

G1251

Abstract: GE NPX intel 8295 Block diagram microprocessor 8097 architecture i386 ex 80287 coprocessor architecture i387 d1251 M8087 M80B
Contextual Info: SÖE D HÔ2bl7S 012S1Û1 4Ô5 • ITL1 INTEL CORP U P / P R P H L S MILITARY ¡387 MATH COPROCESSOR ' T ' i\(\-\Z -Q 5 Full-Range Transcendental Operations for SINE, COSINE, TANGENT, ARCTANGENT and LOGARITHM High Performance 80-Bit Internal Architecture

8250 16550 UART

Abstract: 82360SL D14DD
Contextual Info: A E M Ä N I ! O M FO ^G M Ä T D Ü N in te i 82091AA ADVANCED INTEGRATED PERIPHERAL AIP) Single-Chip PC Compatible I/O Solution for N otebook and Desktop Platforms: — 82078 Floppy Disk Controller Core — Tw o 16550 Compatible UARTs — One Mutti-Function Parallel Port

82371SB

Contextual Info: intei PRELIMINARY 82371FB PIIX AND 82371 SB (PIIX3) PCI ISA IDE XCELERATOR — Independently Programmable for Edge/Level Sensitivity Bridge Between the PCI Bus and ISA Bus PCI and ISA Master/Slave Interface — PCI from 25-33 MHz — ISA from 7.5-8.33 MHz

BD 4913

Abstract: 1k5121 N87C196NT p55g sxc19 8XC196KR 8XC196NT FFA000H P629
Contextual Info: intei a b w a k x s ii uraiFÇ xæ fisiÂTr 8XC196NT CHMOS MICROCONTROLLER WITH 1 MBYTE LINEAR ADDRESS SPACE • 20 MHz Operation ■ O scillator Fail Detection C ircuitry ■ High Performance CHMOS 16-Blt CPU ■ High Speed Peripheral Transaction Server PTS