MFLEBL75 Search Results

FDS 4468

Abstract: HBT 01 - 04G INTEL 486 sx sl pinout 240950 JVC 4580 fds 4418 TOT - 4301 INTEL DX4 241199 Intel DX4TM
Contextual Info: intj, INTEL486 PROCESSOR FAMILY • Write-Back Enhanced lntelDX4™ Processor — Up to 100-MHz Operation — Speed-Multiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Write-Back Cache — Integrated Floating-Point Unit — 3.3V Core Operation with 5V Tolerant

intel i386 ex circuit diagram

Abstract: intel 80368 Instruction set Architecture i386 ex board M82384 i386 dx ICE-386 271052 271062 i386 SL M8088
Contextual Info: SñE J> • intei 462bl75 D I S H E D 17T ¡ITL1 INTEL CORP ÜP/PRPHLS ' T ' L t cv - n - y t - f MILITARY ¡386 HIGH PERFORMANCE 32-BIT MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT Flexible 32-Bit Microprocessor — 8, 16, 32-Bit Data Types — 8 General Purpose 32-Bit Registers

d5017

Abstract: schematic diagram 555 PAM 82820 mch chip 8-pin H049 obd usb api 4st 03 82820 GAR7 H027 MLT 22 542
Contextual Info: intei Intel 820 Chipset: 82820 Memory Controller Hub MCH Datasheet November 1999 Order Number: 290630-001 Mfl2bl75 GEGTTlb Ö5Ö • Intef* 82820 MCH intel. Information in this docum ent is provided In connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

82378IB

Abstract: 82378 apm 8105 ISA/AD 945 SFH 6711 SGDA 290473 BA9S 82C37 82C37A
Contextual Info: O M F Q 3 M rO (M 82378 SYSTEM I/O (SIO • Provides the Bridge Between the PCI Bus and ISA Bus ■ 100% PCI and ISA Compatible — PCI and ISA Master/Slave Interface — Directly Drives 10 PCI Loads and 6 ISA Slots — Supports PCI at 25 MHz and 33 MHz

compal service manual

Abstract: M/1E54H 1E06H
Contextual Info: in tel. APPENDIX C REGISTERS This appendix provides reference information about the device registers. Table C-l lists the mod­ ules and major components of the device with their related configuration and status registers. Ta­ ble C-2 lists the registers, arranged alphabetically by mnemonic, along with their names,

Contextual Info: In te l 28F512 512K 64K x 8 CMOS FLASH MEMORY Flash Electrical Chip-Erase — 1 Second Typical Chip-Erase Quick-Pulse Programming Algorithm — 10 /as Typical Byte-Program — 1 Second Chip-Program 100,000 Erase/Program Cycles 12.0V ± 5 % Vpp High-Performance Read

Contextual Info: Ä E M Ä I M ! DMIFOKßüDATrD !?!!] in te l 28F016XS 16-MBIT 1-MBIT x 16, 2-MBIT x 8 SYNCHRONOUS FLASH MEMORY Effective 0-Wait-State Performance up to 33 MHz Backward Compatible with 28F016SA/SV, 28F008SA Command-Set SmartVoltage Technology — User-Selectable 3.3V or 5V Vcc

82c59a-2

Contextual Info: inte* 82C59A-2 CHMOS Programmable Interrupt Controller Pin Compatible with NMOS 8259A-2 Eight-Level Priority Controller 80C86/88 and 8080/85/86/88 Compatible Expandable to 64 levels Fully Static Design Programmable Interrupt Modes Single 5V Power Supply Low Standby Power—10 jxA

A4232-01

Abstract: 80C251 wsa0 microcontroller intel 8293 Scans-00122849
Contextual Info: [F[^@[D y T iP^i^OiW in te i 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER • Complete Universal Serial Bus Specification compatibility — Supports Isochronous and Non-isochronous data I Power-saving Idle and Powerdown Modes I User-selectable Configurations

Contextual Info: intel. APPENDIX C REGISTERS This appendix provides reference information about the device registers. Table C -l lists the mod­ ules and major components of the device with their related configuration and status registers. Ta­ ble C-2 lists the registers, arranged alphabetically by mnemonic, along with their names,

Contextual Info: in te l P R S U IM IO IiQ A Ifflf 28F016SA 16-MBIT 1 MBIT x 16, 2 MBIT x 8 FlashFile MEMORY • ■ ■ ■ ■ User-Selectable 3.3V or 5V Vcc ■ Revolutionary Architecture User-Configurable x8 or x16 Operation — Pipelined Command Execution 70 ns Maximum Access Time

01ag

Abstract: ML616
Contextual Info: in te l CHAPTER 3 INSTRUCTION SET REFERENCE This chapter describes the complete Intel Architecture instruction set, including the integer, floating-point, MMX technology, and system instructions. The instruction descriptions are arranged in alphabetical order. For each instruction, the forms are given for each operand combi­

bu 2508 af equivalent

Contextual Info: Ä W Ä K l i O M F O ^ K M T F ß ® ! ^ in te i 82378 SYSTEM I/O SIO) Provides the Bridge Between the PCI Bus and ISA Bus 100% PCI and ISA Compatible — PCI and ISA Master/Slave Interface — Directly Drives 10 PCI Loads and 6 ISA Slots — Supports PCI at 25 MHz and 33 MHz

wsa1w

Abstract: microcontroller 87C251 3AD5 272783 QSC family
Contextual Info: P^@ y f Pl^iWQEW in ie l. 8XC251SA/S B/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Commercial/Express I Binary-code Compatible with MCS>® 51 and 8XC251 SB A-step Microcontrollers I Pin Compatible with 44-lead PLCC and 40-lead PDIP MCS 51 Sockets Register-based MCS 251 Architecture

IC GE 6066

Contextual Info: Intel386 SX MICROPROCESSOR • Full 32-Bit Internal Architecture — 8-, 16-, 32-Bit Data Types — 8 General Purpose 32-Bit Registers ■ Runs ln te l 3 8 6 TM Software in a Cost Effective 16-Bit Hardware Environment — Runs Same Applications and O.S.’s

Ap1c-d

Abstract: B2379 82378ZB
Contextual Info: intei 82378ZB SYSTEM I/O SIO AND 82379AB SYSTEM I/O APIC (SIO.A) Provides the Bridge Between the PCI Bus and ISA Bus 100% PCI and ISA Compatible — PCI and ISA Master/Slave Interface — Directly Drives 10 PCI Loads and 6 ISA Slots — PCI at 25 MHz and 33 MHz

Contextual Info: inteJ PKiOBflOMÄl 2-MBIT 128K X 16, 256K X 8 SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY 28F200BV-T/B, 28F200CV-T/B, 28F002BV-T/B • Intel SmartVoltage Technology — 5V or 12V Program/Erase — 3.3V or 5V Read Operation — Increased Programming Throughput

Contextual Info: 28F016SV • SmartVoltage Technology — User-Selectable 3.3V or 5V Vcc — User-Selectable 5V or 12V VPP ■ 65 ns Access Time ■ 1 Million Erase Cycles per Block ■ 30.8 MB/sec Burst Write Transfer Rate ■ 0.48 MB/sec Sustainable Write Transfer Rate ■ Configurable x8 or x16 Operation

Contextual Info: intei 28F016XS Flash Memory 28F016XS 16-MBIT 1 MBIT X 16, 2 MBIT X 8 SYNCHRONOUS FLASH MEMORY Effective Zero W ait-State Performance up to 33 Mhz — Synchronous Pipelined Reads Backwards-Com patible with 28F008SA Com m and-Set 2 [jA Typical Deep Power-Down

Contextual Info: in te i 82596DX AND 82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR Perform s C om plete C S M A /C D Medium Access Control MAC Functions— Independently o f CPU — IEEE 802.3 (EOC) Fram e Delimiting Supports Industry Standard LANs — IEEE TYPE 10BASE-T (TPE),

Contextual Info: PRELIMINARY in te i INTEL 430MX PCISET 82371 MX MOBILE PCI I/O IDE XCELERATOR MPIIX • Provides a Bridge Between the PCI Bus and Extended I/O Bus — PCI Bus; 25-33 MHz — Extended I/O Bus; 7.5-8.33 MHz ■ System Power Management (Intel SMM Support) — Programmable System Management

Contextual Info: in te i A28F256A 256K 32K x 8 CMOS FLASH MEMORY Automotive Extended Automotive Temperature Range -4 0 °C to + 125°C Flash Electrical Chip-Erase — 1 Second Typical Chip-Erase Quick-Pulse Programming Algorithm — 10 fis Typical Byte-Program — 0.5 Second Chip-Program

TB 2929 H alternative

Contextual Info: 82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting ■ Supports Industry Standard LANs — IEEE TYPE 10BASE-T, IEEE TYPE 10BASE5 (Ethernet*),

INTEL 82360

Abstract: intel 82380 82380 lm 3361 82380 dma 82380-16 intel 80386 bus architecture pipeline architecture for 80386 82384 82380-20
Contextual Info: INTEL CORP -CUP/PRPHLS} h?£ 1 • 482^175 0151355=) in te l 82380 HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS ■ High Performance 32-Bit DMA Controller — SO MBytes/sec Maximum Data Transfer Rate at 25 MHz — 8 Independently Programmable