48C20 Search Results

48C20

Abstract: SA125 AT49BV640DT-70CU AT49BV640D AT49BV640DT AT49BV640D-70CU SWITCH SA125 278000 eprom
Contextual Info: Features • Single Voltage Operation Read/Write: 2.65V - 3.6V • Access Time – 70 ns • Sector Erase Architecture • • • • • • • • • • • • • – One Hundred Twenty-seven 32K Word 64K Bytes Main Sectors with Individual Write Lockout

AT49BV6416

Abstract: AT49BV6416C AT49BV6416CT
Contextual Info: Features • 64-megabit 4M x 16 Flash Memory • 2.7V - 3.6V Read/Write • High Performance • • • • • • • • • • • • – Asynchronous Access Time – 70 ns – Page Mode Read Time – 20 ns Sector Erase Architecture – Eight 4K Word Sectors with Individual Write Lockout

FCR16

Abstract: H48C
Contextual Info: 1 << INVERTER V i n vs. Vout IC : 48C20-40 8 CHflRflCTERISTICS » Vdd : 5 [V] 2 1 3 4 5 Vin m r~ 1 << IN VERTER GftlN/PHRSE vs. 1C : H4BC20-40 FR EQ UE NC Y CHflRflCTERISTICS >> Vdd : S CV3 L Gain CdB] Ft - 2 0 . 4 [MHz! P . M “ 116.1 Freq. IMHil Cdeg]

Contextual Info: 48C2000B K CMOS D R A M ELECTRONICS 2 M x 8 B i t CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 2,097,152 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage +5.0V or +3.3V , refresh

Contextual Info: SAM S UN G E L E C T R O N I C S INC b?E D 48C2000L/LL • 7^4142 OOlbSn b3b H S M ä K CMOS DRAM 2 M x 8 Bit CMOS Dynamic RAM with Fast Page Mode FEATURES GENERAL DESCRIPTION • Performance range: The Samsung 48C2000L/LL is a C MOS high speed 2,097,152 b itx S Dynam ic Random Access Memory, it's

IC WORKS

Abstract: S4231 48C20
Contextual Info: 1CWORKS 48C20 ADVANCE INFORMATION, FEBRUARY 1995 Audio Subsystem Clock Generator FEATURES FUNCTIONAL DESCRIPTION Full clock support for add-in sound cards or motherboard sound subsystems Packaged in small 8 pin, 150 mil SOIC 3.3 V or 5.0 V power supply

1004CL

Abstract: 44V16 366F 44C40 372V3280 2100B-7 M5368 KMM5368103B 44v16100 dram module kmm 2mx32
Contextual Info: FUNCTION GUIDE 1. INTRODUCTION DRAM Module I. Single In-Line M em ory M odule SIMM l-i. Fast Page ( FP ) Mode 5 V [T6M~Based j- f — ftM x 3 g "KMM5321200BW/BWG-6 H ~KM M 5321200BW/BWG-&#39; -|lM x 3 6 [2MX32 KMM5322100BKU/BKUG-5 K —[2Mx36 H H | KMM5322100BKÜ/BKÛ g ^K 1<M M 5322-| OOBKU/BKUG3-7

SA97

Abstract: AT49BV640D AT49BV640DT SA1117
Contextual Info: Features • Single Voltage Operation Read/Write: 2.65V - 3.6V • Access Time – 70 ns • Sector Erase Architecture • • • • • • • • • • • • • – One Hundred Twenty-seven 32K Word 64K Bytes Main Sectors with Individual Write Lockout

15j100 capacitor

Abstract: W28NT1000 W48NT600 15j100 RETMA RAILS p022h P012H R36W MARKING CODE WM9 12EB70
Contextual Info: ACOPIAN PROMISES TO SHIP WITHIN THREE DAYS Acopian P.O. Box 638 Easton, PA 18044-0638 . . . and we keep that promise. For more than 40 years, Acopian has been shipping AC to DC power modules within three days after receipt of an order. During this period, the Acopian line has expanded from

Contextual Info: 48C2004C, KM48C2104C KM48V2004C, KM48V2104C CMOS DRAM 2M x 8Bit CMOS Dynamic RAM with Extended Data Out DESCRIPTION This is a fam ily of 2,097,152 x 8 bit Extended Data Out CMOS DRAMs. Extended Data O ut Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power supply voltage +5.0V or +3.3V , refresh cycle (2K Ref. or 4K

hep 154 silicon diode

Abstract: zy 406 transistor motorola HEP 801 hep 154 diode hep R1751 triac zd 607 2sb337 RS5743.3 F82Z hep 230 pnp
Contextual Info: SEMICONDUCTOR This guide has been prepared by the Motorola HEP technical staff to provide a cross-reference for the Hobbyist, Experimenter, and Profes­ sional service technician. The information contained herein is based on an analysis of the published specifications of each device listed. This

AT49BV640D

Abstract: AT49BV640DT SA1117
Contextual Info: Features • Single Voltage Operation Read/Write: 2.65V - 3.6V • Access Time – 70 ns • Sector Erase Architecture • • • • • • • • • • • • • – One Hundred Twenty-seven 32K Word 64K Bytes Main Sectors with Individual Write Lockout

3608B

Abstract: SA117
Contextual Info: Features • Single Voltage Operation Read/Write: 2.65V - 3.6V • Access Time – 70 ns • Sector Erase Architecture • • • • • • • • • • • • • – One Hundred Twenty-seven 32K Word 64K Bytes Main Sectors with Individual Write Lockout

AT49BV640D

Abstract: AT49BV6416C AT49BV6416CT
Contextual Info: Features • 64-megabit 4M x 16 Flash Memory • 2.7V - 3.6V Read/Write • High Performance • • • • • • • • • • • • – Asynchronous Access Time – 70 ns – Page Mode Read Time – 20 ns Sector Erase Architecture – Eight 4K Word Sectors with Individual Write Lockout

l829

Contextual Info: 48C200QA/AL/ALL/ASL . _ C M O S D RAM 2M x 8 Bit CMOS Dynamic RAM with Fast Page Mode FEATURES GENERAL DESCRIPTION • P e rfo rm a n c e ranger tR A C 48C2000A'AL'ALL'ASL-= . 50ns tC A C tR C 1 13ns i 90ns 48C2000A'AL/ALL'ASL-S 60ns KM48C2Q00A&#39;AL/A L L -3 u-7

SA93

Abstract: SA97 AT49BV6416C AT49BV6416CT
Contextual Info: Features • 64-megabit 4M x 16 Flash Memory • 2.7V - 3.6V Read/Write • High Performance • • • • • • • • • • • • – Asynchronous Access Time – 70 ns – Page Mode Read Time – 20 ns Sector Erase Architecture – Eight 4K Word Sectors with Individual Write Lockout

PE 8001A

Abstract: 23C1001 KM41C256P 23C1010 KM41C464P KM68512 km41c256 TFK 805 TFK 001
Contextual Info: MEMORY ICs FUNCTION GUIDE 2. PRODUCT GUIDE 2.1 Dynamic RAM C apacity 256K bit 1M bit O rganization Speed ns T e ch n ology KM41C256P 255K X 1 70/80/100 CMOS Fast Page 16 Pm DIP Now KM41C256J 256 K X 1 70/80/100 CMOS Fast Page 16 Pm PLCC Now KM41C256Z 256Kx 1

SA97

Abstract: AT49BV6416C AT49BV6416CT
Contextual Info: Features • 64-megabit 4M x 16 Flash Memory • 2.7V - 3.6V Read/Write • High Performance • • • • • • • • • • • • – Asynchronous Access Time – 70 ns – Page Mode Read Time – 20 ns Sector Erase Architecture – Eight 4K Word Sectors with Individual Write Lockout

SA128

Contextual Info: Features • Single Voltage Operation Read/Write: 2.65V - 3.6V • Access Time – 70 ns • Sector Erase Architecture • • • • • • • • • • • • • – One Hundred Twenty-seven 32K Word 64K Bytes Main Sectors with Individual Write Lockout