35DMB Search Results

CY7C187

Abstract: CY7C187A
Contextual Info: CY7C187A 64K x 1 Static RAM Features provided by an active LOW chip enable CE and three-state drivers. The CY7C187A has an automatic power-down feature, reducing the power consumption by 55% when deselected. • High speed — 20 ns • CMOS for optimum speed/power

C1507

Abstract: C1504 C1502 c1509 C150 CY7C150 R1329
Contextual Info: CY7C150 1Kx4 Static RAM Features Separate I/O paths eliminates the need to multiplex data in and data out, providing for simpler board layout and faster system performance. Outputs are three-stated during write, reset, deselect, or when output enable OE is held HIGH, allowing for

CY7C128A

Abstract: transistor C128 C128A 7C128A-45 7C128A-25
Contextual Info: 1CY 7C12 8A CY7C128A 2K x 8 Static RAM Features Functional Description • Automatic power-down when deselected • CMOS for optimum speed/power • High speed — 15 ns • Low active power — 440 mW commercial — 550 mW (military) • Low standby power

C167A-3

Abstract: C167A-2 CY7C167A CY7C167A-35DMB cy7c167a-35pc
Contextual Info: CY7C167A 16K x 1 Static RAM Features Functional Description • Automatic power-down when deselected • CMOS for optimum speed/power • High speed — 15 ns • Low active power — 275 mW • Low standby power — 83 mW • TTL-compatible inputs and outputs

CY7C197

Contextual Info: CY7C197 256Kx1 Static RAM Features vided by an active LOW chip enable CE and three-state drivers. The CY7C197 has an automatic power-down feature, reducing the power consumption by 75% when deselected. • High speed — 12 ns Writing to the device is accomplished when the chip enable

CY7C263-35PC

Abstract: 7C261 CY7C263 CY7C26345DMB cerdip z PACKAGE 7C264 C261 CY7C261 CY7C264 f1b0
Contextual Info: CY7C261 CY7C263/CY7C264 CYPRESS Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 20 ns commercial — 25 ns (military) • Low power — 660 mW (commercial) — 770 m\V (military) • Super low standby power (7C261)

0148-t

Abstract: CY7C148 CY7C149 CY7C148-25DC up c1482 0148t L5045 CY7C148-35PC CY7C148-35DC MU 350
Contextual Info: CYPRESS SEMICONDUCTOR MbE D B DODbMll 2 5 0 ^ 2 b EÏCYP CY7C148 CY7C149 CYPRESS SEMICONDUCTOR Automatic power-down when dese­ lected 7C148 CMOS for optimum speed/power 25-ns access time Low active power — 440 mW (commercial) — 60S m\V (military) Low standby power (7C148)

K73 Package

Abstract: 3 phase inverter schematic diagram 7C166 CY7C164A CY7C166A CI64A CY7C164A-45DMB
Contextual Info: 4bE D CYPRESS SEM IC ON DU CT OR □ - p q & eSÛ'IbbE OQObMfiS 2 R3CYP .r S - l O C Y 7 C I6 4 A C Y 7 C 1 6 6 A ";ui'./^CTPRESS , _ SEMICONDUCTOR 16,384 x 4 Static R/W RAM Features Functional Description • Automatic power-down when

7C192-12

Abstract: 7C192-15 7C192-20 A10C CY7C191 CY7C192 CY7C192-25PC
Contextual Info: MbE D CYPRESS SEMICON DUC TOR B 250^fc,b2 OOQfc.1,42 3 E 3 C Y P CY7C191 CY7C192 CYPRESS SEMICONDUCTOR Features • Automatic power-down when deselected • Transparent write 7C19X • CMOS for optimum speed/power • H ighspeed — tM = 25 ns • Low active power

CY7C101A

Abstract: CY7C102A 7C101A-12 l3lx
Contextual Info: PRELIMINARY 9 / C Y PR E SS CY7C101A CY7C102A 256K x 4 Static RAM with Separate I/O Features Functional Description • High speed The CY7C101A and CY7C102A are high­ perform ance CMOS static RAM s orga­ nized as 262,144 x 4 bits with separate I/O. Easy m emory expansion is p rovided by ac­

1S26

Abstract: P4C116 P4C116L AD5e
Contextual Info: PERFORMANCE SEMICONDUCTOR SDE V • 7 0 b 2 5 cl7 0001780 3äb * P S C P4C116/P4C116L ULTRA HIGH SPEED 2K x 8 STATIC CMOS RAMS SCRAMS FEATURES ■ Full CMOS, 6T Cell Single 5V±10% Power Supply ■ High Speed (Equal Access and Cycle Times) -12,15/20/25/35 ns (Commercial)

CY7C167A

Abstract: CY7C167A-35DMB
Contextual Info: CY7C167A '0 CYPRESS 16K x 1 Static RAM Features Functional D escription • Automatic power-down when dese­ lected • CMOS for optimum speed/power • High speed — 15 ns • Low active power — 275 mW • Low standby power — 83 mW • TTL-compatible inputs and outputs

CY7C171-45VC

Abstract: 7C172-35 CY7C171-35PC CY7C171-45DMB A10C CY7C171 CY7C172 7C171-25 CY7C172-35PC 2272 aq
Contextual Info: 4 bE D • 23 3 *^ 2 QDOtSBB =5 E ICYP *0VH <O -V?<y& s? CYPRESS SEMICONDUCTOR CY7C171 CY7C172 4096 x 4 Static R/W RAM Separate I/O R eading th e device is accom plishedby tak­ ing chip enable CE LOW, while write en­ able (W E) remains H IG H . U nder these con­

CY7C225A

Contextual Info: CY7C225A '= C Y P R E S S Features • CMOS for optimum speed/power • High speed — 18 ns address set-up — 12 ns clock to output • Low power — 495 mW commercial — 660 mW (military) • Synchronous and asynchronous out­ put enables • On-chip edge-triggered registers

AB26S

Abstract: 7C109A CY7C109 CY7C109A
Contextual Info: CY7C109A PRELIMINARY l ^wSSQBBSf S S ySSt Ì p YJe JkP XRI- XjiïJF ^ 128KX 8 Static RAM Features Functional Description • H ighspeed The CY7C109A is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable

cy7c131-55nc

Abstract: ZT12 CY7C130 CY7C131 CY7C140 CY7C141 IDT7130 IDT7140
Contextual Info: CY7C130/CY7C131 CY7C140/CY7C141 W CYPRESS Features • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable o f withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation • Master CY7C130/CY7C131 easily ex­

automaticpower change over switch circuit diagram

Abstract: CY7C185 CY7C185A
Contextual Info: CY7C185A '* C YPRESS 8K x 8 Static RAM Features Functional D escription • High speed — 20 ns • CMOS for optimum speed/power T he CY7C185A is a high-perform ance CMOS static RA M organized as 8192 words by 8 bits. Easy mem ory expansion is provided by an active LO W chip enable

P4C148

Abstract: P4C149
Contextual Info: P4C148, P4C149 ULTRA HIGH SPEED 1K x 4 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell Two Options – P4C148 Low Power Standby Mode – P4C149 Fast Chip Select Control High Speed Equal Access and Cycle Times – 10/12/15/20/25/35/45/55 ns (Commercial) – 15/20/25/35/45/55 ns (P4C148 Military)

P4C150

Contextual Info: P4C150 ULTRA HIGH SPEED 1K X 4 RESETTABLE STATIC CMOS RAM FEATURES Separate Input and Output Ports Full CMOS, 6T Cell Three-State Outputs High Speed Equal Access and Cycle Times – 10/12/15/20/25 ns (Commercial) – 15/20/25/35 ns (Military) Fully TTL Compatible Inputs and Outputs

P4C147

Contextual Info: P4C147 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM FEATURES Full CMOS, 6T Cell Single 5V ± 10% Power Supply High Speed Equal Access and Cycle Times – 10/12/15/20/25 ns (Commercial) – 15/20/25/35 ns (Military) Separate Input and Output Ports Three-State Outputs

Contextual Info: CY7C106A PRELIMINARY y CYPRESS 256K x 4 Static RAM Features Functional D escription • High speed T he CY7C106A is a high-perform ance CM O S static R A M organized as 262,144 words by 4 bits. Easy m em ory expansion is provided by an active LO W chip enable

Contextual Info: CY7C148 CY7C149 CYPRESS IK x 4 Static RAM Features • TTL-compatible inputs and outputs • Automatic power-down when dese­ lected 7C148 • CMOS for optimum speed/power • 25-ns access time • Low active power — 440 mW (commercial) — 605 mW (military)

Contextual Info: 7C101A: 11-25-91 Revision: Thursday, February 18,1993 CY7C101A CY7C102A k ' Vwt S3 « 3 PRELIMINARY 7J= CYPRESS SEMICONDUCTOR 256K x 4 Static RAM with Separate I/O Features Functional Description • Highspeed — tAA = 12 ns • Transparent write 7C101A

P4C168

Abstract: P4C169 P4C170
Contextual Info: P4C168, P4C169, P4C170 ULTRA HIGH SPEED 4K x 4 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell Fully TTL Compatible, Common I/O Ports High Speed Equal Access and Cycle Times – 12/15/20/25/35ns (Commercial) – 20/25/35/45/55/70ns (P4C168 Military) Three Options