27LS0 Search Results

27LS02

Abstract: AM27LS03 AM27LS03-30/BEA
Contextual Info: ADV M I C R O {MEflORY} &*\ D e 05 5 7 5 2 0 00BS553 7 0257528 ADV MICRO (MEMORY 890 25553 D T-46-23-08 Am 27LS02/Am 27LS03 H 64-Bit Low-Power Inverting-Output Bipolar RAM > 3 DISTINCTIVE CHARACTERISTICS Fully decoded 16 word x 4-bit low-power Schottky

74s288

Abstract: SIGNETICS 74S188 74S188 74S287 74S474 mmi 6331 74S387 signetics 82s23 H6555 MMI 6349
Contextual Info: S ig n e tic s Memories BIPOLAR M EMORY CROSS R E F E R E N C E AMD' 2700/27 LSOO 2701/27LSÛ 1 27S08/27LS08 27S09/27LS09 27S10 27S11 3101 310 1 A/27S02 93415 93415A 93425 93425A F A IR C H IL D 10149 10144 1 0410 10415 93403 93406 93411 93411A 93415 93415A

74S387

Abstract: 74s288 74S474 74S188 MMI 6381 74S287 27ls09 74S209 MMI 6349 74s201
Contextual Info: Signetics Memories BIPOLAR M EMORY CROSS R E F E R E N C E AMD' 2700/27 LSOO 2701/27LSÛ 1 27S08/27LS08 27S09/27LS09 27S10 27S11 3101 310 1 A/27S02 93415 93415A 93425 93425A F A IR C H IL D 10149 10144 1 0410 10415 93403 93406 93411 93411A 93415 93415A 93417

am27s07

Contextual Info: 27LS06/27LS07 64-Bit Low-Power Noninvsrting-Output Bipolar RAM DISTINCTIVE CHARACTERISTICS • • • • Fully decoded 16-word x 4-bit low power Schottky RAMs Internal ECL circuitry for optimum speed/power perfor­ mance over voltage and temperature Output preconditioned during write to eliminate the write

Contextual Info: CY74S189, 27LS03 CY27S03, CY27S07 CYPRESS SEMICONDUCTOR 16 x 4 Static R /W RAM Features • Three-state outputs • Fully decoded, 16 word x 4-bit high­ speed CMOS RAMs • TTL-compatible inteface levels • Inverting outputs 27S03, 27LS03, 74S189 c o n d itio n e d so th a t th e w rite d a ta is p re s ­

27ls06

Contextual Info: 27LS06/27LS07 64-Bit Low-Power Noninverting-Output Bipolar RAM DISTINCTIVE CHARACTERISTICS • • • Fully decoded 16-word x 4-bit low power Schottky RAMs Internal ECL circuitry for optimum speed/power perfor­ mance over voltage and temperature Output preconditioned during write to eliminate the write

27ls07

Abstract: 27ls06
Contextual Info: Am 27LS06/27LS07 64-Bit Low-Power Noninverting-Output Bipolar RAM • Available with three-state outputs 27LS07 or with open collector outputs (27LS06) Electrically tested and optically inspected die for the assemblers of hybrid products • GENERAL DESCRIPTION

Am27ls00

Abstract: AM27LS01 27LS01 Am27LS01-1
Contextual Info: Am 27LS00/01 Series 256-Bit Low-Power Schottky Bipolar RAM Output preconditioned during write to eliminate the write recovery glitch Available with three-state outputs or with open-collector outputs High speed Internal ECL circuitry for optimum speed/power perfor­

S1095

Abstract: CY27S07A
Contextual Info: CY74S189, 27LS03 CY27S03, CY27S07 CYPRESS SEMICONDUCTOR • Inverting outputs 27S03, 27LS03, 74S189 • Non-Inverting outputs 27S07 • High speed — 25 ns • Low power — 210 mW 27LS03 • Power supply 5V ± 10% • Advanced high-speed CMOS process­

cy27s07almb

Abstract: CY27S07PC 27ls03 74S189 7C189 cy74s189
Contextual Info: CY74S189, 27LS03 CY27S03, CY27S07 CYPRESS SEMICONDUCTOR Features • Fully decoded, 16 word x 4-bit high­ speed CMOS RAMs • Inverting outputs 27S03, 27LS03, 74S189 • Non-inverting outputs 27S07 • High speed — 25 ns • Low power - 210 mW 27LS03

AM27LS03PC

Abstract: 74ls189 ram 27lS03 Am27LS02/27LS03
Contextual Info: 27LS02/27LS03 64-Bit Low-Power Inverting-Output Bipolar RAM Output preconditioned during write to eliminate write recovery glitch Available with open-oollector outputs 27LS02 or with three-state outputs (27LS03> Pin-com patible replacem ents fo r 74LS289, (use

AM27LS02

Abstract: 74ls189 ram
Contextual Info: 27LS02/27LS03 64-Bit Low-Power Inverting-Output Bipolar RAM • • Fully decoded 16 word x 4-bit low-power Schottky RAMs Low Power Internal ECL circuitry for optimum speed/power perfor­ mance over voltage and temperature • • • Output preconditioned during write to eliminate write

27LS00

Abstract: Am27LS00 AM27S00 AM27LS00/BEA
Contextual Info: NOV 2 ì 1991J Page 0001 n / 2 3 / 8 8 14:34:29 Tx: AM 27LS00 TED • Ft: AM D FMT 27LS00 Series 256-Bit Low-Power Schottky Bipolar RAM > 3 D IS T IN C T IV E C H A R A C TER ISTIC S • • High spead Internal ECL circuitry for optimum speed/power perfor­

fmt 150

Abstract: 27LS07
Contextual Info: 2 1 1991 &MI8C ~ P ag* 0001 11/2 8/88 15:41:31 Tx: 27LS07 TED - Ft; AMD FMT Am 27LS07 a 64-Bit Low-Power Noninverting-Output Bipolar RAM DISTINCTIVE CHARACTERISTICS Fully decoded 16-word x 4-bit low-power Schottky RAMs Internal ECL circuitry for optimum speed/power perfor­

sn76131

Abstract: tlo72cp TOSHIBA 2N3055 M53207P 2N3055 TOSHIBA KIA7313AP kia7640ap LA5530 M5L8155P TBB1458B
Contextual Info: ACTIVE ELECTRONICS COMPONENTS CROSS REFERENCE GUIDE 2SC429GTM 2SC458 2SC458LG 2SC503 2SC504 2SC510 2SC512 2SC519 2SC520A 2SC594 2SC699A 2SC780 2SC809-1 2SC945 2SC3012 2SC3074 2SC3114 2SC3115 2SC3116 2SC3117 2SC3134 2SC3135 2SC3138 2SC3143 2SC3144 2SC3145 2SC3157

27LS00

Abstract: AM27S00
Contextual Info: NOV 2 ì 1991J P ag e 0001 n /2 3 /8 8 1 4 :3 4 :2 9 Tx: A M 2 7 L S 0 0 T E D • Ft: A M D F M T 27LS00 Series 256-Bit Low-Power Schottky Bipolar RAM > 3 to DISTINCTIVE CHARACTERISTICS • • High spead Internal ECL circuitry for optimum spee d /p o w e r perfor­

cq 721

Abstract: am26ls31 27LS00 TRANSISTOR SUBSTITUTION Amdasm am2911pc 25S558 STK 025 power amplifier GE semiconductor data handbook am29811adc-b
Contextual Info: í i í i í i n z ta a a a a a a a a a a a r n a a a a a a a a a a a a a i: 33a a a a a a n a a a a a ; a a a a a a a a n a a iia a r r ia a a a a a n a a iia a a r l a n g a s í i í i í i * i¿ w n r w a s a jn sü n n a n a n n n n íiíi íiíiíi n n s n n n

precon sea

Abstract: ls 07
Contextual Info: 2 1 1991 Page 0001 1 1/2 8/88 15:41:31 Tx: 27LS07 TED - Ft: AMO FMT Am 2 7 LS0 7 £1 64-Bit Low-Power Noninverting-Output Bipolar RAM DISTINCTIVE CHARACTERISTICS Fully decoded 16-word x 4-bit low-power Schottky RAMs Internal ECL circuitry for optimum speed/power performane* over voltage and temperature

78015 Ap

Abstract: 27LS07 78015 L78015 7801501
Contextual Info: AMD REVISIONS LTR DATE vn-MO-M DESCRIPTION D Add LCC package t y p e . Add 2 new d e v ic e t y p e s . Change d e v ic e typ e 0 2 . C o n v e rt to m i l i t a r y draw ing fo rm a t. E Change ven dor s i m i l a r p a r t numbers in 6 . 4 . E d i t o r i a l chan ges th ro u g h o u t.

74ls189 ram

Abstract: precon po
Contextual Info: " I — Jk ^ ’g T g ^ 1— mk ^ Page 0001 0 1 /1 6 /8 9 11:16:37 Tx: 27LS03 TED - Ft: A V O PMT woniNMMSflnncMiMCa 27LS03 64-Bit Low-Power Inverting-Output Bipolar RAM > 3 ro DISTINCTIVE CHARACTERISTICS Fully decoded 16 word x 4-bit low-power Schottky

8605104EX

Abstract: 27LS03 27S02 27S03 8605106EX marking 2u03 8605101EX
Contextual Info: REVISIONS LTR DATE YB-MO-OA DESCRIPTION A Update vendor's part number. Change to m ilit a r y drawing format. 1987 JULY 7 E d ito ria l changes throughout. B Made technical changes to table I . Added device types 07, 08, and 09 fo r vendor CAGE 34335. Changes to fig u re s 4 , 5 , and 6 .

6301-1 prom

Abstract: 3622 prom mmi 3601 PROM 3601 intel 3601 PROM PROM intel 3601 9344C N82S141 74S189 N82S137
Contextual Info: BIPOLAR MEMORY DIVISION MAY 1982 8192-BIT BIPOLAR PROM 1024 x 8 82HS181 /82HS181A (T.S.) DESCRIPTION FEATURES The 82HS181 is fie ld p rog ra m m a b le , w h ich m eans th a t cu s to m p a tte rn s are im ­ m e d ia te ly a va ila b le by fo llo w in g th e fu s in g

N82S191

Abstract: 6301-1 prom 82S191 SIGNETICS prom 6331-1 PROM intel 3601 SIGNETICS prom n82s141 74S200 HM76161-5 93427C
Contextual Info: MAY 1982 BIPOLAR MEMORY DIVISION 16,384-BIT BIPOLAR PROM 2048 X 8 DESCRIPTION The 82S191 Is field programmable, which means that custom patterns are Immediate­ ly available by following the fusing proce­ dure given in this data manual. The 82S191 is supplied with all outputs at a logical low.

6301-1 prom

Abstract: MMI 6301-1 93427C 6331-1 MMI 6341-1 dm74s472 PROM intel 3601 DM74S570 MMI 6330 N82S23
Contextual Info: MAY 1982 BIPOLAR MEMORY DIVISION 82HS195 T.S. 16,384-BIT BIPOLAR PROM (4 0 9 6 x 4 ) A d v a n c e Inform ation DESCRIPTION FEATURES The 82H S 19 5 is fie ld p ro g ra m m a b le , w h ic h m e a n s th a t c u s to m p a tte rn s are im m e d i a te ­