XAPP7 Search Results

XAPP7 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
COOLRUNNER-II ucf file Abstract: COOLRUNNER-II examples XC2C32A LVCMOS25 LVCMOS33 level shifter 5V to 3.3V XAPP341 LVCMOS18 LVCMOS15 XAPP785 Contextual Info: Application Note: CoolRunner-II Level Translation Using Xilinx CoolRunner-II CPLDs R XAPP785 v1.0 June 22, 2005 Summary As electronic design has advanced over the years, more and more I/O standards have been created. Since the days when the 5V CMOS and TTL standards were the prevalent standards	Original	xapp785 coolrunner-ii ucf file coolrunner-ii examples xc2c32a +6lvcmos25 lvcmos33 level shifter 5v to 3.3v xapp341 lvcmos18 lvcmos15	PDF
QDR pcb layout Abstract: XAPP750 UG002 CLK180 FF1152 K7R323684M K7R323684M-FC20 XC2VP20 phase control trailing edge schematic D0DCM Contextual Info: Application Note: Virtex-II Series R XAPP750 v1.0 May 24, 2004 Summary QDR II SRAM Local Clocking Interface for Virtex-II Pro Devices Author: Olivier Despaux This application note describes a 200 MHz four-word burst QDR II SRAM interface implemented in a Virtex-II Pro XC2VP20 FF1152 –6 device. This implementation uses local	Original	xapp750 xc2vp20 ff1152 k7r323684m-fc20 +740interface qdr pcb layout ug002 clk180 k7r323684m phase control trailing edge schematic d0dcm	PDF
IDELAY Abstract: XAPP701 xilinx mig user interface design A596 DS302 UG070 XAPP702 X701 Contextual Info: Application Note: Virtex-4 Family R XAPP701 v2.0 March 12, 2007 DDR2 SDRAM Physical Layer Using Direct-Clocking Technique Author: Tze Yi Yeoh Summary This application note describes the DDR2 SDRAM physical layer design using the direct-clocking technique in a VirtexTM-4 device. The direct-clocking technique utilizes some of	Original	xapp701 64-tap idelay xilinx mig user interface design +5a596 ds302 ug070 xapp702 x701	PDF
XAPP759 Abstract: verilog code for fibre channel 1000BASE-X PPC405 Virtex-II Pro and Virtex-II Pro X Platform FPGAs Xuint32 CPCS BOARD POWER SUPPLY ML323 1000base-x xilinx DS264 Contextual Info: Application Note: Virtex-II Pro Family R Configurable Physical Coding Sublayer Author: Dai Huang, Jack Lo, and Shalin Sheth XAPP759 v1.1 March 4, 2005 Summary This application note describes a Configurable Physical Coding Sublayer (CPCS) reference design that extends the functionality of the Xilinx RocketIO multi-gigabit transceiver (MGT)	Original	xapp759 xapp662 com/bvdocs/appnotes/xapp662 xapp672 +13com/bvdocs/appnotes/xapp672 ds083 com/bvdocs/publications/ds083 ml321 verilog code for fibre channel 1000base-x ppc405 virtex-ii pro and virtex-ii pro x platform fpgas xuint32 cpcs board power supply ml323 1000base-x xilinx ds264	PDF
XC4VLX25-FF668 Abstract: MT49H16M18FM-25 XAPP701 XC4VLX25 xilinx mig user interface design xc4vlx25ff668 X710 XAPP710 xilinx mig 020421 Contextual Info: Application Note: Virtex-4 Family R XAPP710 v1.4 April 28, 2008 Synthesizable CIO DDR RLDRAM II Controller for Virtex-4 FPGAs Author: Benoit Payette Summary This application note describes how to use a Virtex -4 device to interface to Common I/O (CIO) Double Data Rate (DDR) Reduced Latency DRAM (RLDRAM II) devices. The reference design	Original	xapp710 xc4vlx25-ff668 mt49h16m18fm-25 xapp701 +6xc4vlx25 xilinx mig user interface design xc4vlx25ff668 x710 xilinx mig 020421	PDF
ISERDES Abstract: ISERDES spartan 6 OSERDES SRL16 XAPP721 Contextual Info: Application Note: Virtex-4 FPGAs R XAPP721 v2.2 July 29, 2009 High-Performance DDR2 SDRAM Interface Data Capture Using ISERDES and OSERDES Author: Maria George Summary This application note describes a data capture technique for a high-performance DDR2 SDRAM interface. This technique uses the Input Serializer/Deserializer (ISERDES) and Output	Original	xapp721 64-bit 72-bit iserdes +3iserdes spartan 6 oserdes srl16	PDF
XAPP753 Abstract: ISERDES OSERDES TMSC6000 RAMB16 TMS320C64xx cpu XC4VLX25 microblaze block architecture IPC-2141 NEWNES RADIO Contextual Info: Interfacing Xilinx FPGAs to TI DSP Platforms Using the EMIF Application Note XAPP753 v2.0.1 January 29, 2007 R R Xilinx is disclosing this Specification to you solely for use in the development of designs to operate on Xilinx FPGAs. Except as stated herein,	Original	xapp753 ipc-2141 ipc-d-317a 0-13-084408-x +8iserdes oserdes tmsc6000 ramb16 tms320c64xx cpu xc4vlx25 microblaze block architecture newnes radio	PDF
XAPP799 Abstract: Port Expander 32 bit COOLRUNNER-II example led XC2C32A i2c master verilog code GP10 LVCMOS15 LVCMOS25 LVCMOS33 verilog code for I2C MASTER slave Contextual Info: Application Note: CPLD R An SMBus/I2C-Compatible Port Expander XAPP799 v1.1.1 June 4, 2008 Summary Today’s microcontrollers and microprocessors often limit the number of General Purpose I/O (GPIO) ports in order to conserve pin count and to reduce package sizes. Unfortunately, for	Original	xapp799 xc2c32a port expander 32 bit coolrunner-ii example led +6i2c master verilog code gp10 lvcmos15 lvcmos25 lvcmos33 verilog code for i2c master slave	PDF
vhdl code for lvds driver Abstract: XC2VP20FF896 XC2VP20-FF896 XAPP230 XAPP268 XAPP756 prbs pattern generator using vhdl MULT18X18S ROCKETIO 320M Contextual Info: Application Note: Virtex-II Pro Family Transmitting DDR Data Between LVDS and RocketIO CML Devices R XAPP756 v1.0 November 4, 2004 Author: Martin Kellermann Summary The serial transfer of data between devices on a board or cards on a backplane using the LVDS	Original	xapp756 xapp268 ug024 xapp230 +7vhdl code for lvds driver xc2vp20ff896 xc2vp20-ff896 prbs pattern generator using vhdl mult18x18s rocketio 320m	PDF
C5-M3 Abstract: XAPP715 XC4VLX15 Contextual Info: Application Note: Virtex-4 and Virtex-II Pro FPGAs R Multiple Bit Error Correction Author: Simon Tam XAPP715 v1.0 November 15, 2004 Summary In high-reliability aerospace, avionics, and military applications, single error correction (SEC) and double error detection (DED) may not provide adequate protection against SDRAM	Original	xapp715 ee387 edu/class/ee387/2003/rm c5-m3 +1xc4vlx15	PDF
12-bit ADC interface vhdl code for FPGA Abstract: 12-bit ADC interface vhdl complete code for FPGA verilog code for 8 bit shift register theory IPC-2141 VHDL code for high speed ADCs using SPI with FPGA ADC Verilog Implementation XAPP268 XAPP774 emif vhdl fpga XAPP623 Contextual Info: Application Note: Virtex-II, Virtex-II Pro, and Spartan-3 Families Connecting Xilinx FPGAs to Texas Instruments ADS527x Series ADCs R XAPP774 v1.2 February 23, 2006 Author: Marc Defossez Summary This application note describes how to connect a high-speed Texas Instruments (TI) ADS5273	Original	ads527x xapp774 ads5273 12-bit +912-bit adc interface vhdl code for fpga 12-bit adc interface vhdl complete code for fpga verilog code for 8 bit shift register theory ipc-2141 vhdl code for high speed adcs using spi with fpga adc verilog implementation xapp268 emif vhdl fpga xapp623	PDF
XAPP678C Abstract: XAPP678 XAPP688 MT49H8M36 MT49H8M36FM-33 XAPP688C XAPP771 synchronous fifo design in verilog RLDRAM MT49H8M36FM-33 IT Contextual Info: Application Note: Virtex-II Pro Devices R XAPP771 v1.0 June 13, 2005 Synthesizable CIO DDR RLDRAM II Controller for Virtex-II Pro FPGAs Author: Rodrigo Angel Summary This application note describes how to use a Virtex -II Pro device to interface to Common I/O	Original	xapp771 xapp678c xapp688c xapp688 +9ug141 ml367 com/userguides/ug141 xapp678 mt49h8m36 mt49h8m36fm-33 synchronous fifo design in verilog rldram mt49h8m36fm-33 it	PDF
vhdl source code for i2c optic Abstract: IPC-2141 TZA3015HW william orr tza3015 register electronica digital RF transmitter dr1 CLK180 XAPP265 XAPP268 Contextual Info: Application Note: Virtex-II and Virtex-II Pro Families Connecting Xilinx FPGAs to the Philips A-rate Fibre Optic Transceiver R XAPP764 v1.0 May 25, 2004 Summary This application note shows how a Xilinx Virtex -II or Virtex-II Pro™ device can connect to a	Original	xapp764 tza3015hw 0-13-084408-x vhdl source code for i2c optic +8ipc-2141 william orr tza3015 register electronica digital rf transmitter dr1 clk180 xapp265 xapp268	PDF
xilinx mig user interface design Abstract: OSERDES 128 MB DDR2 SDRAM ddr2 ram XAPP721 XAPP723 Contextual Info: Application Note: Virtex-4 FPGAs R XAPP723 v1.4 October 17, 2007 DDR2 Controller (267 MHz and Above) Using Virtex-4 Devices Author: Karthi Palanisamy Summary DDR2 SDRAM devices offer new features that go beyond the DDR SDRAM specification and enable the DDR2 device to operate at data rates of 666 Mb/s. High data rates require higher	Original	xapp723 64-bit 72-nit xilinx mig user interface design +4oserdes 128 mb ddr2 sdram ddr2 ram xapp721	PDF

2VP20 Abstract: 2VP70 2VP30 2vp40 DS083 PPC405 XAPP755 powerpc 405 CPMC405CLOCK 2VP100 Contextual Info: Application Note: Virtex-II Pro Family PowerPC 405 Clock Macro for -7 C and -6(I) Speed Grade Dual-Processor Devices R XAPP755 (v1.2) February 8, 2006 Summary Author: Kraig Lund The embedded PowerPC 405 processor blocks in Virtex-II Pro™ devices with -7 speed	Original	xapp755 xc2vp100 2vp20 2vp70 +72vp30 2vp40 ds083 ppc405 powerpc 405 cpmc405clock 2vp100	PDF
ML403 Abstract: verilog for 8 point dct in xilinx Xint32 UART ml403 vhdl vga IDCT Virtex-4 Platform FPGAs TFT APU FCM PPC405 UG073 Contextual Info: Application Note: Virtex-4 FX Family Accelerated System Performance with the APU Controller and XtremeDSP Slices R XAPP717 v1.1.1 Sept. 29, 2005 Author: Harn Hua Ng and Latha Pillai Summary Portions of certain software applications that are implemented in software can run faster by	Original	xapp717 ppc405 dsp48 sobvdocs/userguides/ug082 +11ug111 ug073 com/bvdocs/userguides/ug073 ml403 verilog for 8 point dct in xilinx xint32 uart ml403 vhdl vga idct virtex-4 platform fpgas tft apu fcm	PDF
XAPP702 Abstract: 128 MB DDR2 SDRAM ddr2 ram ISERDES XAPP701 XAPP721 Contextual Info: Application Note: Virtex-4 Family R DDR2 Controller Using Virtex-4 Devices Author: Tze Yi Yeoh XAPP702 v1.8 April 23, 2007 Summary DDR2 SDRAM devices offer new features that surpass the DDR SDRAM specifications and enable a DDR2 device to operate at data rates of 400 Mb/s and above. High data rates demand	Original	xapp702 128 mb ddr2 sdram ddr2 ram iserdes +2xapp701 xapp721	PDF
XAPP779 Abstract: UG156 SRL16 voter UG002 XQR2V6000 XQR2V1000 2V1000 Contextual Info: Application Note: Virtex-II FPGAs R XAPP779 v1.1 February 19, 2007 Summary Correcting Single-Event Upsets in Virtex-II Platform FPGA Configuration Memory Authors: Brendan Bridgford, Carl Carmichael, Chen Wei Tseng Designers of space-based application must be concerned with the effect of single-event upsets	Original	xapp779 ug156 srl16 voter +4ug002 xqr2v6000 xqr2v1000 2v1000	PDF
TLH-4986 Abstract: Rayovac BR1225 tadiran XAPP766 Data Encryption Standard DES efuse Ralf BR1225 Rayovac Contextual Info: Application Note: Virtex-II Series R XAPP766 v1.0 July 8, 2004 Using High Security Features in Virtex-II Series FPGAs Author: Ralf Krueger Summary This application note shows how a designer can very simply implement a battery with the Virtex -II series FPGAs for high bitstream security. It shows a number of Xilinx recommended	Original	xapp766 tlh-4986 rayovac br1225 tadiran +5data encryption standard des efuse ralf br1225 rayovac	PDF
verilog code for longest prefix matching Abstract: vhdl code for longest prefix matching longest prefix matching algorithm code longest prefix matching algorithm ML403 verilog code 8 bit LFSR PPC405 RAMB16 XAPP738 XC4VFX12 Contextual Info: Application Note: Virtex-4 FPGA Family Code Acceleration with an APU Coprocessor: a Case Study of an LPM Algorithm R XAPP738 v1.0 February 22, 2008 Summary Contact: Glenn Steiner In network address routing, an IP packet is routed to a specific destination based on its IP	Original	xapp738 verilog code for longest prefix matching vhdl code for longest prefix matching longest prefix matching algorithm code +6longest prefix matching algorithm ml403 verilog code 8 bit lfsr ppc405 ramb16 xc4vfx12	PDF
ML405 Abstract: "Galois Field Multiplier" verilog RAID6 SATA hard disk controller XILINX ML405 DS11 DSP48 PPC405 XAPP535 XAPP731 Contextual Info: Application Note: Virtex-4 Family R XAPP731 v1.1 March 20, 2007 Summary Hardware Accelerator for RAID6 Parity Generation / Data Recovery Controller Author: Matt DiPaolo A Redundant Array of Independent Disks (RAID) array is a hard-disk drive (HDD) array where	Original	xapp731 library/3298 xapp535 com/bvdocs/appnotes/xapp535 +12xapp536 com/bvdocs/appnotes/xapp536 ug073 com/bvdocs/appnotes/ug073 ml405 galois field multiplier" verilog raid6 sata hard disk controller xilinx ml405 ds11 dsp48 ppc405	PDF
verilog code of prbs pattern generator Abstract: free verilog code of prbs pattern generator verilog code 16 bit LFSR in PRBS VHDL CODE FOR 16 bit LFSR in PRBS verilog code 16 bit LFSR verilog code 8 bit LFSR in scrambler vhdl code for 16 prbs generator vhdl code 16 bit LFSR prbs pattern generator prbs using lfsr Contextual Info: Application Note: Virtex-4 Family of FPGAs R Virtex-4 RocketIO Bit-Error Rate Tester Author: Vinod Kumar Venkatavaradan XAPP713 v1.1 April 18, 2007 Summary This application note describes the implementation of a Virtex -4 RocketIO™ bit-error rate tester (XBERT) reference design. The XBERT reference design generates and verifies nonencoded or 8B/10B-encoded high-speed serial data on one or multiple point-to-point links	Original	xapp713 8b/10b-encoded 40-bit verilog code of prbs pattern generator +9free verilog code of prbs pattern generator verilog code 16 bit lfsr in prbs vhdl code for 16 bit lfsr in prbs verilog code 16 bit lfsr verilog code 8 bit lfsr in scrambler vhdl code for 16 prbs generator vhdl code 16 bit lfsr prbs pattern generator prbs using lfsr	PDF
XAPP778 Abstract: interrupt controller vhdl code download 0X0700 interrupt controller in vhdl code interrupt controller vhdl code interrupt in embedded system PPC405 Xuint32 RS232-UART microblaze Contextual Info: Application Note: Embedded Hardware Systems R XAPP778 v1.0 January 11, 2005 Using and Creating Interrupt-Based Systems Author: Paul Glover Summary This application note describes how to properly set up external and internal interrupts in an embedded hardware system. Use of an interrupt controller to manage more than one interrupt	Original	xapp778 interrupt controller vhdl code download 0x0700 interrupt controller in vhdl code +6interrupt controller vhdl code interrupt in embedded system ppc405 xuint32 rs232-uart microblaze	PDF
Applications of "XOR Gate" Abstract: mixed signal fpga datasheet XAPP776 Pulse generator circuit Contextual Info: Application Note: Virtex-II Pro X Family R XAPP776 v1.0 April 4, 2005 AC Coupling Bypass for High-Speed Digitizing on Virtex-II Pro X FPGAs Author: Tim Hagen Summary This application note describes a method for bypassing the AC coupling in Virtex -II Pro X	Original	xapp776 applications of "xor gate mixed signal fpga datasheet pulse generator circuit	PDF

XAPP7 Search Results

XAPP7 Datasheets Context Search

COOLRUNNER-II ucf file

QDR pcb layout

IDELAY

XAPP759

XC4VLX25-FF668

ISERDES

XAPP753

XAPP799

vhdl code for lvds driver

C5-M3

12-bit ADC interface vhdl code for FPGA

XAPP678C

vhdl source code for i2c optic

xilinx mig user interface design

2VP20

ML403

XAPP702

XAPP779

TLH-4986

verilog code for longest prefix matching

ML405

verilog code of prbs pattern generator

XAPP778

Applications of "XOR Gate"